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參數(shù)資料
| 型號(hào)： | CD74HC373 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 有三態(tài)輸出的8個(gè)透明D型鎖存器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | CD74HC373 |
Philips Semiconductors
Product data
CBT16211
24-bit bus switch with 12-bit output enables
2001 Jun 13
5
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
SYMBOL
PARAMETER
FROM
(INPUT)
TO
V
CC
= 5.0 V
±
0.5 V
UNIT
(OUTPUT)
Min
Max
t
pd
Propagation delay
1
A or B
B or A
—
0.25
ns
t
en
Output enable time
to High and Low level
OE
A or B
1.5
6.0
ns
t
dis
Output disable time
from High and Low level
OE
A or B
1.5
6.0
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V.
INPUT
1.5 V
OUTPUT
t
PLH
t
PHL
SA00028
1.5 V
1.5 V
1.5 V
3 V
0 V
V
OH
V
OL
Waveform 1. Input (An) to Output (Yn) Propagation Delays
Output Control
(Low-level
enabling )
1.5 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
3.5 V
0 V
V
OL
+ 0.3 V
V
OH
– 0.3 V
SA00029
1.5 V
1.5 V
1.5 V
0 V
3 V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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