參數(shù)資料
型號： CD74HC194NSR
廠商： Texas Instruments, Inc.
元件分類： 通用總線功能
英文描述： High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
中文描述： 高速CMOS邏輯4位雙向通用移位寄存器
文件頁數(shù)： 6/13頁
文件大?。?/td> 339K
代理商： CD74HC194NSR
6
Set-up Time
S1, S0 to Clock (Figure 4)
t
SU
-
4.5
20
-
25
-
30
-
ns
Set-up Time
DSL, DSR to Clock (Figure 4)
t
SU
-
4.5
14
-
18
-
21
-
ns
Hold Time
S1, S0 to Clock (Figure 4)
t
H
-
4.5
0
-
0
-
0
-
ns
Hold Time
Data to Clock (Figure 3)
t
H
-
4.5
0
-
0
-
0
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay,
Clock to Output (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
Propagation Delay,
Clock to Q
t
PLH
, t
PHL
-
5
14
-
-
-
ns
Output Transition Time
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
Propagation Delay,
MR to Output (Figure 2)
t
PHL
C
L
= 50pF
2
-
140
175
210
ns
4.5
-
28
35
42
ns
6
-
24
30
36
ns
Input Capacitance
C
IN
-
-
-
10
10
10
pF
Maximum Clock Frequency
f
MAX
-
5
60
-
-
-
MHz
Power Dissipation
Capacitance (Notes 4, 5)
C
PD
-
5
55
-
-
-
pF
HCT TYPES
Propagation Delay,
Clock to Output (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
4.5
-
37
46
56
ns
Propagation Delay,
Clock to Q
t
PLH
, t
PHL
-
5
15
-
-
-
ns
Output Transition Times
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
4.5
-
15
19
22
ns
Propagation Delay,
MR to Output (Figure 2)
t
PHL
C
L
= 50pF
4.5
-
40
50
60
ns
Input Capacitance
C
IN
-
-
-
10
10
10
pF
Maximum Clock Frequency
f
MAX
-
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 4, 5)
C
PD
-
5
60
-
-
-
pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per gate.
5. P
D
= V
CC2
f
i
+
∑
(C
L
V
CC2
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Prerequisite For Switching Function
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
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