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參數(shù)資料
| 型號： | CD74HC192PW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters |
| 中文描述： | 高速CMOS邏輯預(yù)置同步4位向上/向下計數(shù)器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 355K |
| 代理商： | CD74HC192PW |
9
FIGURE 2. ’HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS
FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
Test Circuits and Waveforms
(Continued)
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
PRESET DATA
P0
P1
P2
P3
CLOCK UP
CLOCK DOWN
OUTPUTS
Q
0
Q
1
Q
2
Q
3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
0
13
14
15
0
1
2
COUNT DOWN
COUNT UP
RESET
1
0
15
14
13
PRESET
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BINARY THIRTEEN.
3. COUNT UP TO FOURTEEN,
FIFTEEN, TERMINAL COUNT UP,
ZERO, ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN,
FIFTEEN, FOURTEEN AND
THIRTEEN.
NOTES:
1. Master reset overrides load data and clock inputs.
2. When counting up, clock-down input must be high.
When counting down, clock-up input must be high.
CPU OR CPD
l/f
MAX
INPUT LEVEL
V
S
V
S
V
S
t
PHL
t
PLH
V
S
Q
n
V
S
t
W
INPUT LEVEL
TCU OR TCD
t
PHL
t
PLH
V
S
V
S
CPU OR CPD
V
S
V
S
INPUT LEVEL
INPUT LEVEL
INPUT LEVEL
CPU OR CPD
V
S
V
S
t
PLH
Q
n
V
S
t
W
V
S
V
S
V
S
t
W
Pn
PL
t
PHL
t
REC
V
S
MR
CPU OR CPD
Q
n
t
PHL
V
S
V
S
INPUT LEVEL
t
REC
INPUT LEVEL
V
S
V
S
t
W
CD54/74HC192, CD54/74HC193, CD54/74HCT193
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