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參數(shù)資料
| 型號： | CD74FCT541SM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | BiCMOS FCT Interface Logic, Octal Buffers/Line Drivers, Three-State |
| 中文描述： | 聯(lián)邦首都的BiCMOS邏輯接口，八路緩沖器/線路驅(qū)動器，三態(tài) |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 36K |
| 代理商： | CD74FCT541SM |
8-6
Test Circuits and Waveforms
NOTE:
8. Pulse Generator for All Pulses: Rate
≤
1.0MHz; Z
OUT
≤
50
;
t
f
, t
r
≤
2.5ns.
FIGURE 1. TEST CIRCUIT
FIGURE 2. ENABLE AND DISABLE TIMING
FIGURE 3. PROPAGATION DELAY
NOTES:
9. V
OLP
is measured with respect to a ground reference near the output under test. V
OHV
is measured with respect to V
OH
.
10. Input pulses have the following characteristics:
P
RR
≤
1MHz, t
r
= 2.5ns, t
f
= 2.5ns, skew 1ns.
11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1
μ
F capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 4. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
3V
0
DUT
PULSE Z
O
GEN
7V
500
R
L
50pF
500
R
L
V
CC
R
T
R
T
= Z
O
V
0
C
L
V
I
t
r
, t
f
= 2.5ns
(NOTE 8)
SWITCH POSITION
TEST
SWITCH
t
PLZ
, t
PZL
, Open Drain
t
PHZ
, t
PZH
, t
PLH
, t
PHL
DEFINITIONS:
C
L
= Load capacitance, includes jig and probe
capacitance.
R
T
= Termination resistance, should be equal to Z
OUT
of
the Pulse Generator.
V
IN
= 0V to 3V.
Input: t
r
= t
f
= 2.5ns (10% to 90%), unless otherwise specified
Closed
Open
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH
SWITCH
OPEN
t
PZL
3.5V
1.5V
1.5V
0V
t
PLZ
t
PHZ
t
PZH
0V
3.5V
0.3V
0.3V
V
OL
V
OH
SWITCH
CLOSED
ENABLE
DISABLE
1.5V
3V
0V
1.5V
3V
0V
t
PLH
SAME PHASE
INPUT TRANSITION
t
PHL
t
PLH
t
PHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
1.5V
V
OL
V
OH
OTHER
OUTPUTS
OUTPUT
UNDER
TEST
V
OH
V
OL
V
OH
V
OHV
V
OLP
V
OL
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