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參數(shù)資料
| 型號： | CD74ACT164M96 |
| 元件分類： | 通用總線功能 |
| 英文描述： | SHIFT REGISTER|ACT-CMOS|SOP|14PIN|PLASTIC |
| 中文描述： | 移位寄存器|行為的CMOS |專科| 14PIN |塑料 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 86K |
| 代理商： | CD74ACT164M96 |
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B
–
JANUARY 2001
–
REVISED MAY 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
10%
tf
50%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
510%
tf
50%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
Input
In-Phase
Output
50% VCC
tPLH
tPHL
510%
50%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
Open
GND
R1 = 500
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
Output
Control
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈
VCC
0 V
50% VCC
20% VCC
50% VCC
≈
0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC
50% VCC
80% VCC
VCC
R2 = 500
When VCC = 1.5 V, R1 = R2 = 1 k
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
VCC
0 V
CLR
Input
CLK
50% VCC
VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
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