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參數(shù)資料
| 型號： | CD74ACT109E |
| 元件分類： | 通用總線功能 |
| 英文描述： | J-K-Type Flip-Flop |
| 中文描述： | JK -型觸發(fā)器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 86K |
| 代理商： | CD74ACT109E |
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B
–
JANUARY 2001
–
REVISED MAY 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
10%
tf
50%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
510%
tf
50%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
Input
In-Phase
Output
50% VCC
tPLH
tPHL
510%
50%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
Open
GND
R1 = 500
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
Output
Control
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈
VCC
0 V
50% VCC
20% VCC
50% VCC
≈
0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC
50% VCC
80% VCC
VCC
R2 = 500
When VCC = 1.5 V, R1 = R2 = 1 k
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
VCC
0 V
CLR
Input
CLK
50% VCC
VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD74ACT109E WAF | 制造商:Harris Corporation 功能描述: |
| CD74ACT109EE4 | 功能描述:觸發(fā)器 Dual Pos-Edge Trig J-K F-F w/Set-Res RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD74ACT109EG4 | 功能描述:IC JK TYPE POS TRG DUAL 16DIP 制造商:texas instruments 系列:74ACT 包裝:管件 零件狀態(tài):在售 功能:設(shè)置（預(yù)設(shè)）和復位 類型:JK 型 輸出類型:差分 元件數(shù):2 每元件位數(shù):1 時鐘頻率:100MHz 不同 V，最大 CL 時的最大傳播延遲:10.3ns @ 5V，50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高，低:24mA，24mA 電壓 - 電源:4.5 V ~ 5.5 V 電流 - 靜態(tài)（Iq):4μA 輸入電容:10pF 工作溫度:-55°C ~ 125°C（TA） 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 基本零件編號:74ACT109 標準包裝:25 |
| CD74ACT109EN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CD74ACT109ER2489 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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