參數(shù)資料
型號(hào): CD74AC175E
廠商: Texas Instruments, Inc.
英文描述: Quad D Flip-Flop with Reset
中文描述: 四D觸發(fā)器的復(fù)位觸發(fā)器
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 35K
代理商: CD74AC175E
6
Propagation Delay, MR to Q, Q
t
PLH
, t
PHL
1.5
-
-
139
-
-
153
ns
3.3
4.4
-
15.5
4.3
-
17.1
ns
5
3.2
-
11.1
3.1
-
12.2
ns
Input Capacitance
C
I
-
-
-
10
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 13)
-
-
55
-
-
55
-
pF
ACT TYPES
Propagation Delay, CP to Qn
t
PLH
, t
PHL
5
(Note 12)
3
-
10.5
2.9
-
11.5
ns
Propagation Delay, MR to Qn
t
PLH
, t
PHL
5
3.3
-
11.8
3.3
-
13
ns
Input Capacitance
C
I
-
-
-
10
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 13)
-
-
55
-
-
55
-
pF
NOTES:
22. Limits tested 100%.
23. 3.3V Min is at 3.6V, Max is at 3V.
24. 5V Min is at 5.5V, Max is at 4.5V.
25. C
PD
is used to determine the dynamic power consumption per flip-flop.
P
D
= C
PD
V
CC2
f
i
+
Σ
(C
L
+ V
CC
2 f
o
) + V
CC
I
CC
where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
=
supply voltage.
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
FIGURE 7.
FIGURE 8. PROPAGATION DELAY TIMES
Switching Specifications
Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case)
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
INPUT LEVEL
CP
GND
V
S
t
W
t
PHL
t
PLH
V
S
V
S
V
S
V
S
INPUT LEVEL
GND
INPUT
CP
MR
V
S
t
W
t
REM
t
PHL
Q
V
S
V
S
V
S
Q
INPUT LEVEL
GND
D
CP
V
S
t
SU
(L)
t
H
(L)
t
H
(H)
t
SU
(H)
V
S
V
S
V
S
V
S
V
S
INPUT LEVEL
GND
DUT
OUTPUT
R
L
(NOTE)
500
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
CC
= 1.5V, R
L
= 1k
.
CD74AC
CD74ACT
Input Level
V
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
CD74AC175, CD74ACT175
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