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參數(shù)資料
| 型號(hào)： | CD7343CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FM STEREO MULTIPLEX DECODER |
| 中文描述： | 調(diào)頻立體聲多路解碼器 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | CD7343CS |
Silicore
CD7343CS
SHAOXING SILICORE TECHNOLOGY CO.,LTD
www. Silicore. com. cn
CHMC
3/5
TEST CIRCUIT
10uF
SW1
6
~
SG
1
3
1
R
9
4
1
330K
3
L
2
1
S
2.2uF
Vcc=8V
~
Hz
3
0
3
0
4.7uF
4.7uF
SW3
SW3
SW2
BPF
3.3K
V3
~
Hz
IN
CD7343CS
9
1
2
3
4
5
6
7
8
C1
C2
C4
R2
R
BPF: 19kHz
55dB 38kHz
55dB L.P.F
APPLICATION INFORMATION (refer to test circuit)
External Components
1.
Input coupling capacitor (C1)
The recommended value is 10
μ
F. If smaller values than 10
μ
F are used, low
frequency separation will worsens, and if large values are used ,POP noise occurs
strongly.
2. Low Pass Filter (C2, C1, R1)
This is the low Pass filter for the PLL, which is determined the capture range
and THD at low frequency.
3. VCO network (C4, R2, R7)
The VCO free running frequency is adjusted by connecting a frequency counter
to monitor the 38kHz output of Pin6 .
4. Decoder Output (Pin8,9)
These components provide Right and Left channel Output load circuits . The
recommended circuits as follows:
4.7uF
3
1nF
400mH
2.2K
6
68nF
From
Pin 8,9
Output
4.7uF
3
From
Pin 8,9
Output
1
LPF
19kHz<55dB
38kHz<55dB
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