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參數(shù)資料
| 型號： | CD54HC4059F3A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter |
| 中文描述： | 高速CMOS邏輯CMOS可編程分頻氮計數(shù)器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 209K |
| 代理商： | CD54HC4059F3A |
3
How to Preset the HC/HCT4059 to Desired
÷
N
The value N is determined as follows:
To calculate preset values for any N count, divide the N
count by the Mode. The resultant is the corresponding
preset values of the 5th through 2nd decade with the
remainder being equal to the 1st decade value.
NOTE: To verify the results, use Equation 1:
N = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4
N = 8479
N = (MODE
) (1000 x Decade 5 Preset + 100 x Decade 4
Preset + 10 x Decade 3 Preset + 1 x Decade 2 Preset) +
Decade 1 Preset
MODE = First counting section divider (10, 8, 5, 4 or 2)
(EQ. 1)
Preset Value =
N
Mode
Example:
N = 8479, Mode = 5
1695 + 4 (Preset Values)
5 | 8479
Mode
N
Mode Select = 5
K
a
K
b
H
L
K
c
H
(EQ. 2)
Program Jam Inputs (BCD)
J1
L
J2
L
J3
H
J4
H
4
1
J5
H
J6
L
J7
H
J8
L
5
J9
H
J10
J11
L
J12
H
L
9
J13
L
J14
H
J15
H
J16
L
6
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FIRST
COUNTING
SECTION
÷
10, 8, 5, 4, 2
LAST
COUNTING
SECTION
÷
1, 2, 2, 4, 8
÷
10
÷
10
÷
10
RECOGNITION
GATING
PRESET
ENABLE
INTERMEDIATE COUNTING SECTION
OUTPUT
STAGE
MODE
CONTROL
PRESETTABLE LOGIC
GND
V
CC
12
24
CLOCK
INPUT
1
MODE
SELECT
INPUTS
14
13
11
K
a
K
b
K
c
LATCH
ENABLE
2
DIVIDE-BY-N
OUTPUT
23
P.E.
J1
3
J2
4
J3
5
J4
6
J5
22
J6
21
J7
20
J8
19
J9
18
J10
17
J11
16
J12
15
J13
10
J14
9
J15
8
J16
7
PROGRAM JAM INPUTS (BCD)
CD54HC4059, CD74HC4059
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