參數(shù)資料
型號(hào)： CD54HC4024F3A
廠商： Texas Instruments, Inc.
元件分類： 通用總線功能
英文描述： High-Speed CMOS Logic 7-Stage Binary Ripple Counter
中文描述： 高速CMOS邏輯7級(jí)二進(jìn)制紋波計(jì)數(shù)器
文件頁(yè)數(shù)： 5/11頁(yè)
文件大?。?/td> 283K
代理商： CD54HC4024F3A
5
Reset Pulse Width
t
W
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
HCT TYPES
Maximum Input Pulse
Frequency
f
MAX
4.5
25
-
20
-
16
-
MHz
Input Pulse Width
t
W
4.5
20
-
25
-
30
-
ns
Reset Recovery Time
t
REC
4.5
10
-
13
-
15
-
ns
Reset Pulse Width
t
W
4.5
20
-
25
-
30
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
CTO125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay Time
(Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
140
-
175
-
210
ns
CP to Q1’ Output
4.5
-
-
28
-
35
-
42
ns
C
L
=15pF
5
-
11
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
24
-
30
-
36
ns
Q
n
to Q
n
+ 1
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
C
L
=15pF
5
-
6
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
13
-
13
-
19
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
5
-
14
-
-
-
-
-
ns
6
-
-
29
-
27
-
43
ns
Output Transition Time
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
IN
C
L
= 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
C
L
=15pF
5
-
30
-
-
-
-
-
pF
HCT TYPES
Propagation Delay Time
(Figure 2)
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
40
-
50
-
60
ns
CP to Q1’ Output
C
L
=15pF
5
-
17
-
-
-
-
-
ns
Q
n
to Q
n
+ 1
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
C
L
=15pF
5
-
6
-
-
-
-
-
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
40
-
50
-
60
ns
C
L
=15pF
5
-
17
-
-
-
-
-
ns
Prerequisite for Switching Specifications
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
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