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參數(shù)資料
| 型號： | CD54HC32W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High Speed CMOS Logic Quad 2-Input OR Gate |
| 中文描述： | 高速CMOS邏輯四路2輸入或門 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 45K |
| 代理商： | CD54HC32W |
5
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 5, 6)
C
PD
-
5
-
22
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
RHL
, t
PHL
C
L
= 50pF
4.5
-
-
24
-
30
-
36
ns
PropagationDelay,DataInputto
Output Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
9
-
-
-
-
-
ns
Transition Times (Figure 2)
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 5, 6)
C
PD
-
5
-
22
-
-
-
-
-
pF
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per gate.
6. P
D
= V
CC2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications
Input t
r
, t
f
= 6ns
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54HCT32, CD74HC32, CD74HCT32
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