參數(shù)資料
型號(hào)： CD54HC195F3A
廠商： Texas Instruments, Inc.
元件分類： 通用總線功能
英文描述： High-Speed CMOS Logic 4-Bit Parallel Access Register
中文描述： 高速CMOS邏輯4位并行訪問注冊(cè)
文件頁數(shù)： 4/11頁
文件大小： 335K
代理商： CD54HC195F3A
4
Prerequisite For Switching Function
PARAMETER
SYMBOL
TEST
CONDITIONS V
CC
(V)
-
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Clock Frequency
f
MAX
2
6
-
5
-
4
-
MHz
4.5
30
-
25
-
20
-
MHz
6
35
-
29
-
23
-
MHz
MR Pulse Width
t
w
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
Clock Pulse Width
t
w
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
Set-up Time
J, K, PE to Clock
t
SU
-
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
Hold Time
J, K, PE to Clock
t
H
-
2
3
-
3
-
3
-
ns
4.5
3
-
3
-
3
-
ns
6
5
-
3
-
3
-
ns
Removal Time,
MR to Clock
t
REM
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay, CP to
Output
t
PLH
, t
PHL
C
L
= 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
Propagation Delay,
MR toOutput
t
PLH
, t
PHL
C
L
= 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
Output Transition Times
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
Input Capacitance
C
IN
-
-
-
10
10
10
pF
CP to Q
n
Propagation Delay
t
PLH
, t
PHL
C
L
= 15pF
5
14
-
-
-
ns
MR to Q
n
t
PHL
C
L
= 15pF
5
13
-
-
-
ns
Maximum Clock Frequency
f
MAX
C
L
= 15pF
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 2, 3)
C
PD
C
L
= 15pF
45
-
-
-
pF
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per flip-flop.
3. P
D
= V
CC2
f
i
+
∑
(C
L
V
CC2
+ f
O
) where f
i
= Input Frequency, f
O
= Output Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
CD54HC195, CD74HC195
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