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參數(shù)資料
| 型號： | CD54HC195 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed CMOS Logic 4-Bit Parallel Access Register |
| 中文描述： | 高速CMOS邏輯4位并行訪問注冊 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 335K |
| 代理商： | CD54HC195 |
2
Functional Diagram
TRUTH TABLE
OPERATING MODES
INPUTS
OUTPUT
MR
CP
PE
J
K
Dn
Q
0
Q
1
Q
2
Q
3
Q
3
Asynchronous Reset
L
X
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
↑
h
h
h
X
H
q
0
q
1
q
2
q
2
Shift, Reset First Stage
H
↑
h
l
l
X
L
q
0
q
1
q
2
q
2
Shift, Toggle First Stage
H
↑
h
h
l
X
q
0
q
0
q
1
q
2
q
2
Shift, Retain First Stage
H
↑
h
l
h
X
q
0
q
0
q
1
q
2
q
2
Parallel Load
H
↑
l
X
X
dn
d
0
d
1
d
2
d3
d2
H = High Voltage Level
L = Low Voltage Level,
X = Don’t Care
↑
= Transition from Low to High Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,
dn (q
n
) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock
Transition.
11
Q
3
1
2
10
3
J
CP
K
MR
15
14
13
12
9
4
5
6
7
Q
0
Q
1
Q
2
Q
3
D
0
D
1
D
2
D
3
PE
CD54HC195, CD74HC195
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