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參數(shù)資料
| 型號： | CD54HC00H |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High Speed CMOS Logic Quad 2-Input NAND Gate |
| 中文描述： | 高速CMOS邏輯四路2輸入與非門 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 266K |
| 代理商： | CD54HC00H |
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
2
-
20
-
40
μ
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
- 0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
- 4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
±
0.1
-
±
1
-
±
1
μ
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
2
-
20
-
40
μ
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
μ
A
NOTE:
2. For dual-supply systems theorectical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
nA
1.8
nB
1.1
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Specifica-
tions table, e.g. 360
μ
A max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
90
-
115
-
135
ns
4.5
-
-
18
-
23
-
27
ns
6
-
-
15
-
20
-
23
ns
PropagationDelay,DataInputto
Output Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
7
-
-
-
-
-
pF
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00
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