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參數(shù)資料
| 型號(hào)： | CD54AC541F3A |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Octal Buffer/Line Driver Three-State, Non-Inverting |
| 中文描述： | AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大小： | 21K |
| 代理商： | CD54AC541F3A |
4
ACT Input Load Table
INPUT
UNIT LOAD
Data
0.5
OE1, OE2
1.3
NOTE: Unit load is
I
CC
limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case)
PARAMETER
SYMBOL
V
CC
(V)
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
AC TYPES
Propagation Delay, Data to Output
t
PLH
, t
PHL
1.5
-
-
98
ns
3.3 (Note 9)
3.3
-
10.9
ns
5 (Note 10)
2.3
-
7.8 (Note 8)
ns
Propagation Delay, Enable, Disable to
Output
t
PZL
, t
PZH
1.5
-
-
150
3.3
5.4
-
18
5
3.6
-
12 (Note 8)
t
PLZ
, t
PHZ
1.5
-
-
150
3.3
4.5
-
15
5
3.6
-
12 (Note 8)
Minimum (Valley) V
OH
During Switching
of Other Outputs
(Output Under Test Not Switching)
V
OHV
See Figure 1
5
-
4 at 25
o
C
-
V
Maximum (Peak) V
OL
During Switching of
Other Outputs
(Output Under Test Not Switching)
V
OLP
See Figure 1
5
-
1 at 25
o
C
-
V
Three-State Output Capacitance
C
O
C
I
-
-
-
15
pF
Input Capacitance
-
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
60
-
pF
ACT TYPES
Propagation Delay, Data to Output
t
PLH
, t
PHL
t
PLZ
, t
PZL
,
t
PZH
, t
PHZ
V
OHV
See Figure 1
5 (Note 10)
2.5
-
8.3 (Note 8)
ns
Propagation Delay, Enable, Disable to
Output
5
4
-
13.4 (Note 8)
ns
Minimum (Valley) V
OH
During Switching
of Other Outputs
(Output Under Test Not Switching)
5
-
4 at 25
o
C
-
V
Maximum (Peak) V
OL
During Switching of
Other Outputs
(Output Under Test Not Switching)
V
OLP
See Figure 1
5
-
1 at 25
o
C
-
V
Three-State Output Capacitance
C
O
C
I
-
-
-
15
pF
Input Capacitance
-
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
60
-
pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max si at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V
11. C
PD
is used to determine the dynamic power consumption per gate.
AC: P
D
= V
CC2
f
i
(C
PD
+ C
L
)
ACT: P
D
= V
CC2
f
i
(C
PD
+ C
L
) + V
CC
I
CC
where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
CD54AC541F3A, CD54ACT541F3A
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