參數(shù)資料
型號(hào): CD54AC00F3A
廠商: HARRIS SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad 2-Input NAND Gate
中文描述: AC SERIES, QUAD 2-INPUT NAND GATE, CDIP14
文件頁(yè)數(shù): 3/4頁(yè)
文件大?。?/td> 24K
代理商: CD54AC00F3A
3
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
1.5
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
V
12
3
-
0.36
-
0.5
V
24
4.5
-
0.36
(Note 5)
-
0.5
(Note 5)
V
50
(Note 6, 7)
5.5
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
±
0.1
(Note 5)
-
±
1
(Note 5)
μ
A
Quiescent Device Current
I
CC
0
5.5
-
4
(Note 5)
-
80
(Note 5)
μ
A
ACT TYPES
High Level Input Voltage
V
IH
-
-
4.5 to 5.5
2
(Note 5)
-
2
(Note 5)
-
V
Low Level Input Voltage
V
IL
-
-
4.5 to 5.5
-
0.8
(Note 5)
-
0.8
(Note 5)
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
4.5
4.4
-
4.4
-
V
-24
4.5
3.94
(Note 5)
-
3.7
(Note 5)
-
V
-50
(Note 6, 7)
5.5
-
-
3.85
-
V
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
4.5
-
0.1
-
0.1
V
24
4.5
-
0.36
(Note 5)
-
0.5
(Note 5)
V
50
(Note 6, 7)
5.5
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
±
0.1
(Note 5)
-
±
1
(Note 5)
μ
A
Quiescent Device Current
I
CC
V
CC
or
GND
0
5.5
-
4
(Note 5)
-
80
(Note 5)
μ
A
AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to 5.5
-
2.4
-
3
mA
NOTES:
5. Tested at 100%.
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum transmission-line-drive capability of 75
for 54AC/ACT Series.
ACT Input Load Table
INPUT
UNIT LOAD
All
0.15
NOTE: Unit load is
I
CC
limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25
o
C.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
CD54AC00F3A, CD54ACT00F3A
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