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參數(shù)資料
| 型號： | CD4724BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 8-Bit Addressable Latch(CMOS 8 位可設定地址的鎖存器) |
| 中文描述： | 的CMOS 8位可尋址鎖存器（的CMOS 8位可設定地址的鎖存器） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 109K |
| 代理商： | CD4724BMS |
7-1267
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4724BMS
CMOS 8-Bit Addressable Latch
Pinout
CD4724BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
Q0
Q1
Q2
VSS
Q3
VDD
WRITE DISABLE
DATA
Q7
Q6
Q5
Q4
RESET
8
DECODER
4
5
6
7
9
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
14
13
WRITE DISABLE
DATA
A0
A1
A2
RESET
VDD = 16
VSS = 8
8
1
2
3
Features
High Voltage Type (20V Rating)
Serial Data Input
Active Parallel Output
Storage Register Capability
Master Clear
Can Function as Demultiplexer
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Multi-line Decoders
A/D Converters
Description
CD4724BMS 8-bit addressable latch is a serial-input, parallel-
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is
addressed (by means of inputs A0, A1, A2) and when WRITE
DISABLE is at a low level. When WRITE DISABLE is high, data
entry is inhibited; however, all 8 outputs can be continuously
read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a high
level. When RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8 demultiplexer; the bit
that is addressed has an active output which follows that data
input, while all unaddressed bits are held to a logic “0” level.
The CD4724BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
December 1992
File Number
3348
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| CD4724BNSR | 功能描述:閉鎖 CMOS 8B Addressable Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BNSRE4 | 功能描述:閉鎖 CMOS 8B Addressable Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BNSRG4 | 功能描述:閉鎖 CMOS 8B Addressable Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BPW | 功能描述:閉鎖 CMOS 8B Addressable Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BPWE4 | 功能描述:閉鎖 CMOS 8B Addressable Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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