參數(shù)資料
型號: CD4556BMS
廠商: Intersil Corporation
英文描述: CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers(CMOS 雙路十進制4選1譯碼器/多路分解器)
中文描述: CMOS雙二進制的1 4解碼器/解復用器(的CMOS雙路十進制4選1譯碼器/多路分解器)
文件頁數(shù): 5/11頁
文件大?。?/td> 96K
代理商: CD4556BMS
7-1253
Specifications CD4555BMS, CD4556BMS
Final Test
Group A
Group B
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
Subgroups 1, 2 3
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
MIL-STD-883
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
PART NUMBER
Static Burn-In 1
Note 1
Static Burn-In 2
Note 1
Dynamic Burn-
In Note 1
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
±
5%, VDD = 18V
±
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
±
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
±
0.5V
OPEN
GROUND
VDD
9V
±
-0.5V
OSCILLATOR
50kHz
25kHz
CD4555BMS & CD4556BMS
4 - 7, 9 - 12
1 - 3, 8, 13 - 15
16
4 - 7, 9 - 12
8
1 - 3, 13 - 16
-
1, 8, 15
16
4 - 7, 9 - 12
2, 14
3, 13
Logic Diagrams
FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS)
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
VDD
VSS
*
ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
5(11)
6(10)
7(9)
Q0
Q1
Q2
Q3
2(14)
3(13)
1(15)
A
B
E
*
*
*
VDD
VSS
*
ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK
4(12)
5(11)
6(10)
7(9)
Q0
Q1
Q2
Q3
2(14)
3(13)
1(15)
A
B
E
*
*
*
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