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參數(shù)資料
| 型號： | CD4541BH |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CMOS PROGRAMMABLE TIMER HIGH VOLTAGE TYPES(20V RATING) |
| 中文描述： | 可編程定時(shí)器的CMOS高電壓類型（20V的評價(jià)） |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 93K |
| 代理商： | CD4541BH |
1
Data sheet acquired from Harris Semiconductor
SCHS085
CD4541B
CMOS Programmable Timer
High Voltage Types (20V Rating)
Features
Low Symmetrical Output Resistance, Typically 100
at V
DD
= 15V
Built-In Low-Power RC Oscillator
Oscillator Frequency Range. . . . . . . . . . DC to 100kHz
External Clock (Applied to Pin 3) can be Used Instead
of Oscillator
Operates as 2
N
Frequency Divider or as a Single-
Transition Timer
Q/Q Select Provides Output Logic Level Flexibility
AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation
Operates With Very Slow Clock Rise and Fall Times
Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range
Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
5V, 10V, and 15V Parametric Ratings
Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”
Description
CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C compo-
nents (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.
The output from this timer is the Q or Q output from the 8th,
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see Truth Table). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2
N
.
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2
N-1
counts
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.
Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUTO RESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, V
DD
should
be greater than 5V.
The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:
Pinout
CD4541B (CERDIP, PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CD4541BF
-55 to 125
14 Ld CERDIP
F14.3
CD4541BE
-55 to 125
14 Ld PDIP
E14.3
CD4541BH
-55 to 125
Chip
-
CD4541BM
-55 to 125
14 Ld SOIC
M14.15
f =
TC
TC
----------------------------------
Where f is between 1kHz
and 100kHz
and R
S
10k
≥
and
2R
TC
≈
R
TC
C
TC
R
S
NC
AUTO RESET
MASTER RESET
V
SS
V
DD
B
A
NC
MODE
Q/Q SELECT
OUTPUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1998
File Number
1378.1
[ /Title
(CD45
41B)
/Sub-
ject
(CMO
S Pro-
gram-
mable
Timer
High
Volt-
age
Types
(20V
Rat-
ing))
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
mili-
tary,
mil
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