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參數(shù)資料
| 型號(hào)： | CD4538BM |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Quadruple Operational Amplifier 14-TSSOP 0 to 70 |
| 中文描述： | 雙精密單穩(wěn)態(tài) |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 237K |
| 代理商： | CD4538BM |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, and t
r
e
t
f
e
20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
TLH
, t
THL
Output Transition Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Trigger OperationD
A or B to Q or Q
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Reset OperationD
C
D
to Q or Q
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Pin 2 or 14
Other Inputs
100
50
40
200
100
80
ns
ns
ns
t
PLH
, t
PHL
Propagation Delay Time
300
150
100
600
300
220
ns
ns
ns
250
125
95
500
250
190
ns
ns
ns
t
WL
, t
WH
Minimum Input Pulse Width
A, B, or C
D
35
30
25
70
60
50
ns
ns
ns
t
RR
Minimum Retrigger Time
0
0
0
ns
ns
ns
0
C
IN
Input Capacitance
10
5
pF
pF
7.5
PW
OUT
Output Pulse Width (Q or Q)
(
Note:
For Typical Distribution,
seeFigure 9)
R
X
e
100 k
X
C
X
e
0.002
m
F
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
208
211
216
226
230
235
244
248
254
m
s
m
s
m
s
R
X
e
100 k
X
C
X
e
0.1
m
F
8.83
9.02
9.20
9.60
9.80
10.00
10.37
10.59
10.80
ms
ms
ms
R
X
e
100 k
X
C
X
e
10.0
m
F
0.87
0.89
0.91
0.95
0.97
0.99
1.03
1.05
1.07
s
s
s
Pulse Width Match between
Circuits in the Same Package
C
X
e
0.1
m
F, R
X
e
100 k
X
Operating Conditions
R
X
e
100 k
X
C
X
e
0.1
m
F
g
1
g
1
g
1
%
%
%
R
X
C
X
*
AC parameters are guaranteed by DC correlated testing.
**
The maximum usable resistance R
X
is a function of the leakage of the Capacitor C
X
, leakage of the CD4538B, and leakage due to board layout, surface
resistance, etc.
External Timing Resistance
External Timing Capacitance
5.0
0
**
k
X
pF
No Limit
Logic Diagram
TL/F/6000–3
FIGURE 1
4
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