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參數(shù)資料
| 型號： | CD4515BCWM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Latched/4-to-16 Line Decoders |
| 中文描述： | 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SOIC-24 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 84K |
| 代理商： | CD4515BCWM |
www.fairchildsemi.com
6
C
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch/decoder to effect a complex data
routing system. A total of 16 inputs from data registers are
selected and transferred via a 3-STATE data bus to a data
distributor for rearrangement and entry into 16 output regis-
ters. In this way sequential data can be re-routed or inter-
mixed according to patterns determined by data select and
distribution inputs.
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the 3-STATE data bus. A fourth
signal, labelled Dis, disables one of the CD4512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1
–
16, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is 8
times faster than the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers.
Information from the 3-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INA
–
IND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, A
–
P. This distribution of data bits to the output
registers can be made in many complex patterns. For
example, all of the most significant bits from the input regis-
ters can be routed into output register A, all of the next
most significant bits into register B, etc. In this way horizon-
tal, vertical, or other methods of data slicing can be imple-
mented.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4514BCWMX | 4-To-16-Line Demultiplexer |
| CD4515BCWMX | 4-To-16-Line Demultiplexer |
| CD4514BMS | CMOS 4-Bit Latch/4-to-16 Line Decoders(CMOS 4位鎖存器/4-16線譯碼器) |
| CD4516BC | BCD-to-7 Segment Latch/Decoder/Driver |
| CD4517 | CMOS DUAL 64-STAGE STATIC SHIFT REGISTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4515BCWMX | 制造商:Fairchild Semiconductor Corporation 功能描述:Latch/Decoder/Demultiplexer Single 4-to-16 24-Pin SOIC W T/R |
| CD4515BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CD4515BD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD4515BE | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 4-Bit Latch/Line RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CD4515BEE4 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 CMOS 4B Latch/4-to- 16 Line Decoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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