參數(shù)資料
型號(hào): CD4060BC
廠商: National Semiconductor Corporation
元件分類: 通用總線功能
英文描述: 14-Stage Ripple Carry Binary Counters(14級(jí)脈動(dòng)帶進(jìn)位二進(jìn)制計(jì)數(shù)器)
中文描述: 14級(jí)波紋卡里二進(jìn)制計(jì)數(shù)器(14級(jí)脈動(dòng)帶進(jìn)位二進(jìn)制計(jì)數(shù)器)
文件頁(yè)數(shù): 3/6頁(yè)
文件大?。?/td> 136K
代理商: CD4060BC
DC Electrical Characteristics
40XXBC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40
§
C
a
25
§
C
a
85
§
C
Units
Min
Max
Min
Typ
Max
Min
Max
V
OH
High Level Output Voltage V
DD
e
5V
4.95
9.95
14.95
4.95
9.95
14.95
5
4.95
9.95
14.95
V
V
V
V
DD
e
10V
V
DD
e
15V
10
15
V
IL
Low Level Input Voltage
V
DD
e
5V, V
O
e
0.5V or 4.5V
V
DD
e
10V, V
O
e
1.0V or 9.0V
V
DD
e
15V, V
O
e
1.5V or 13.5V
1.5
3.0
4.0
2
4
6
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
V
IH
High Level Input Voltage
V
DD
e
5V, V
O
e
0.5V or 4.5V
V
DD
e
10V, V
O
e
1.0V or 9.0V
V
DD
e
15V, V
O
e
1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
I
OL
Low Level Output Current V
DD
e
5V, V
O
e
0.4V
(See Note 3)
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
V
DD
e
10V, V
O
e
0.5V
V
DD
e
15V, V
O
e
1.5V
I
OH
High Level Output Current V
DD
e
5V, V
O
e
4.6V
(See Note 3)
b
0.52
b
1.3
b
3.6
b
0.44
b
1.1
b
3.0
b
0.88
b
2.25
b
8.8
b
0.36
b
0.9
b
2.4
mA
mA
mA
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
I
IN
Input Current
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
b
0.30
0.30
b
10
b
5
b
0.30
10
b
5
b
1.0
1.0
m
A
m
A
0.30
AC Electrical Characteristics
*
CD4020BM/CD4020BC, CD4040BM/CD4040BC
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k, t
r
e
t
f
e
20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL1
, t
PLH1
Propagation Delay Time to Q
1
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
250
100
75
550
210
150
ns
ns
ns
t
PHL
, t
PLH
Interstage Propagation Delay Time
from Q
n
to Q
n
a
1
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
150
60
45
330
125
90
ns
ns
ns
t
THL
, t
TLH
Transition Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
t
WL
, t
WH
Minimum Clock Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
125
50
40
335
125
100
ns
ns
ns
t
rCL
, t
fCL
Maximum Clock Rise and Fall Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
No Limit
No Limit
No Limit
ns
ns
ns
f
CL
Maximum Clock Frequency
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
1.5
4
5
4
MHz
MHz
MHz
10
12
t
PHL(R)
Reset Propagation Delay
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
100
80
450
210
170
ns
ns
ns
t
WH(R)
Minimum Reset Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
100
80
450
210
170
ns
ns
ns
C
in
Average Input Capacitance
Any Input
5
7.5
pF
C
pd
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
50
pF
3
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