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參數(shù)資料
| 型號(hào)： | CD4049UBKNSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS Hex Buffer/Converter |
| 中文描述： | 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大小： | 203K |
| 代理商： | CD4049UBKNSR |
11
FN3315.1
March 6, 2007
CD4049UBMS
Ceramic Metal Seal Flatpack Packages (Flatpack)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
-D-
-C-
0.004
H A - B
M
D
S
S
-A-
-B-
0.036
H A - B
M
D
S
S
e
E
A
Q
L
D
A
A
E1
SEATING AND
BASE PLANE
L
E2
E3
E3
-H-
b
C
S1
M
c1
b1
(c)
(b)
SECTION A-A
BASE
METAL
LEAD FINISH
PIN NO. 1
ID AREA
M
K16.A
MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.440
-
11.18
3
E
0.245
0.285
6.22
7.24
-
E1
-
0.315
-
8.00
3
E2
0.130
-
3.30
-
-
E3
0.030
-
0.76
-
7
e
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
16
16
-
Rev. 1 2-20-95
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4049UBMS | CMOS Hex Buffer/Converter(CMOS 六緩沖器/轉(zhuǎn)換器) |
| CD4049 | CMOS HEX BUFFERS/CONVERTERS |
| CD4050UBDT | 320 x 240 pixel format, CFL backlight available with power harness |
| CD4050NSR | Quad Channel, 3/1, 150Mbps, Digital Isolator 16-SOIC -40 to 125 |
| CD4049 | Hex Inverting,Non-Inverting Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4049UBM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4049UBM96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4049UBMJ/883 | 制造商:National Semiconductor Corporation 功能描述:Buffer/Converter 6-CH Inverting CMOS 16-Pin CDIP |
| CD4049UBMW/883 | 制造商:National Semiconductor Corporation 功能描述:Buffer/Converter 6-CH Inverting CMOS 16-Pin CDIP |
| CD4049UBMW/883C | 制造商: 功能描述: 制造商:undefined 功能描述: |
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