參數(shù)資料
型號: CD4034BC
廠商: National Semiconductor Corporation
英文描述: Replaced by ISO124 :
中文描述: 8級三態(tài)雙向并行/串行輸入/輸出總線注冊
文件頁數(shù): 9/12頁
文件大小: 198K
代理商: CD4034BC
Applications
(Continued)
Shift Right/Shift Left with Parallel Inputs
TL/F/5963–15
Shift left input must be disabled during parallel entry.
A ‘‘High’’ (‘‘Low’’) on the Shift Left/Shift Right input allows
serial data on the Shift Left Input (Shift Right Input) to enter
the register on the positive transition of the clock signal. A
‘‘high’’ on the ‘‘A’’ Enable Input disables the ‘‘A’’ parallel
data lines on Registers 1 and 2 and enables the ‘‘A’’ data
lines on Registers 3 and 4 and allows parallel data into Reg-
isters 1 and 2. Other logic schemes may be used in place of
registers 3 and 4 for parallel loading.
When parallel inputs are not used Registers 3 and 4 and
associated logic are not required.
9
相關PDF資料
PDF描述
CD4034BM
CD4034BMS CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register(CMOS 8級 靜態(tài)雙向串/并輸入/輸出總線寄存器)
CD4035BMS CMOS 4 -Stage Parallel In/Parallel Out Shift Register(CMOS 4級并入并出移位寄存器)
CD4035 Replaced by ISO124 : Low Cost, High Voltage, Wide Bandwidth Standard Hermetic DIP Signal Isolation Buffer Amplifiers 16-CDIP SB
CD4035 4-Bit Parallel-In/Parallel-Out Shift Register
相關代理商/技術參數(shù)
參數(shù)描述
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