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參數(shù)資料
| 型號(hào)： | CD4029BC |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable Binary/Decade Up/Down Counter(可預(yù)置的二進(jìn)制/十進(jìn)制可逆計(jì)數(shù)器) |
| 中文描述： | 可預(yù)置二進(jìn)制/十年加/減計(jì)數(shù)器（可預(yù)置的二進(jìn)制/十進(jìn)制可逆計(jì)數(shù)器） |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 164K |
| 代理商： | CD4029BC |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200 k, Input t
rCL
e
t
fCL
e
20 ns, unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PRESET ENABLE OPERATION
t
PHL
or t
PLH
Propagation Delay Time
to Q output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
285
115
95
570
230
195
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
400
165
135
800
330
260
ns
ns
ns
t
WH
Minimum Preset Enable
Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
80
30
25
160
60
50
ns
ns
ns
t
REM
Minimum Preset Enable
Removal Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
150
60
50
300
120
100
ns
ns
ns
CARRY INPUT OPERATION
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
265
110
90
530
220
180
ns
ns
ns
t
PHL
, t
PLH
Propagation Delay Time
to Carry Output
C
L
e
15 pF
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
85
70
400
170
140
ns
ns
ns
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OH
and I
OL
are tested one output at a time.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application note,
AN-90.
Connection Diagram
Dual-In-Line Package
TL/F/5960–2
Top View
Order Number CD4029B
4
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