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參數(shù)資料
| 型號： | CD4027BCN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 中文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 65K |
| 代理商： | CD4027BCN |
www.fairchildsemi.com
4
C
D
40
27BC
AC Electrical Characteristics (Note 8)
TA = 25°C, CL = 50 pF, trCL = tfCL = 20 ns, unless otherwise specified
Note 8: AC Parameters are guaranteed by DC correlated testing.
Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
Typical Applications
Ripple Binary Counters
Shift Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL or tPLH
Propagation Delay Time
VDD = 5V
200
400
ns
from Clock to Q or Q
VDD = 10V
80
160
VDD = 15V
65
130
tPHL or tPLH
Propagation Delay Time
VDD = 5V
170
340
ns
from Set to Q or Reset to Q
VDD = 10V
70
140
VDD = 15V
55
110
tPHL or tPLH
Propagation Delay Time
VDD = 5V
110
220
ns
from Set to Q or
VDD = 10V
50
100
Reset to Q
VDD = 15V
40
80
tS
Minimum Data Setup Time
VDD = 5V
135
270
ns
VDD = 10V
55
110
VDD = 15V
45
90
tTHL or tTLH
Transition Time
VDD = 5V
100
200
ns
VDD = 10V
50
100
VDD = 15V
40
80
fCL
Maximum Clock Frequency
VDD = 5V
2.5
5
MHz
(Toggle Mode)
VDD = 10V
6.2
12.5
VDD = 15V
7.6
15.5
trCL or tfCL
Maximum Clock Rise
VDD = 5V
15
s
and Fall Time
VDD = 10V
10
VDD = 15V
5
tW
Minimum Clock Pulse
VDD = 5V
100
200
ns
Width (tWH = tWL)VDD = 10V
40
80
VDD = 15V
32
65
tWH
Minimum Set and
VDD = 5V
80
160
ns
Reset Pulse Width
VDD = 10V
30
60
VDD = 15V
25
50
CIN
Average Input Capacitance
Any Input
5
7.5
pF
CPD
Power Dissipation Capacity
Per Flip-Flop
35
pF
(Note 9)
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