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參數(shù)資料
| 型號： | CD4027BC |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual J-K Master/Slave Flip-Flop with Set and Reset(帶置位和復(fù)位的雙J-K主從觸發(fā)器) |
| 中文描述： | 雙JK主/從觸發(fā)器的設(shè)置和復(fù)位（帶置位和復(fù)位的雙JK主從觸發(fā)器） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 58K |
| 代理商： | CD4027BC |
www.fairchildsemi.com
4
C
AC Electrical Characteristics
(Note 8)
T
A
=
25
°
C, C
L
=
50 pF, t
rCL
=
t
fCL
=
20 ns, unless otherwise specified
Symbol
Parameter
Note 8:
AC Parameters are guaranteed by DC correlated testing.
Note 9:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
Typical Applications
Ripple Binary Counters
Shift Registers
Conditions
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Any Input
200
400
ns
from Clock to Q or Q
80
65
160
130
ns
ns
t
PHL
or t
PLH
Propagation Delay Time
170
340
ns
from Set to Q or Reset to Q
70
140
ns
55
110
50
110
220
100
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time
from Set to Q or
Reset to Q
Minimum Data Setup Time
40
135
80
270
ns
ns
t
S
55
45
100
110
90
200
ns
ns
ns
t
THL
or t
TLH
Transition Time
50
40
5
100
80
ns
ns
MHz
f
CL
Maximum Clock Frequency
2.5
(Toggle Mode)
6.2
7.6
15
12.5
15.5
MHz
MHz
μ
s
μ
s
μ
s
ns
t
rCL
or t
fCL
Maximum Clock Rise
and Fall Time
10
5
t
W
Minimum Clock Pulse
Width (t
WH
=
t
WL
)
100
200
40
32
80
80
65
160
ns
ns
ns
t
WH
Minimum Set and
Reset Pulse Width
30
25
5
60
50
7.5
ns
ns
pF
C
IN
C
PD
Average Input Capacitance
Power Dissipation Capacity
Per Flip-Flop
(Note 9)
35
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4027BCM | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BCMX | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BCN | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4027BD/3 | 制造商:RCA 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Ceramic, DIP |
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