參數(shù)資料
型號(hào)： CD4022BCN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs
中文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP RING COUNTER, PDIP16
封裝： PLASTIC, DIP-16
文件頁(yè)數(shù)： 3/8頁(yè)
文件大小： 165K
代理商： CD4022BCN
DC Electrical Characteristics
CD4017BC, CD4022BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40
§
C
Min
a
25
§
Typ
a
85
§
C
Min
Units
Max
Min
Max
Max
V
IL
Low Level
Input Voltage
l
I
O
l
k
1.0
m
A
V
DD
e
5V, V
O
e
0.5V or 4.5V
V
DD
e
10V, V
O
e
1.0V or 9.0V
V
DD
e
15V, V
O
e
1.5V or 13.5V
l
I
O
l
k
1.0
m
A
V
DD
e
5V, V
O
e
0.5V or 4.5V
V
DD
e
10V, V
O
e
1.0V or 9.0V
V
DD
e
15V, V
O
e
1.5V or 13.5V
V
DD
e
5V, V
O
e
0.4V
V
DD
e
10V, V
O
e
0.5V
V
DD
e
15V, V
O
e
1.5V
V
DD
e
5V, V
O
e
4.6V
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
V
IH
High Level
Input Voltage
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
V
V
V
I
OL
Low Level Output
Current (Note 3)
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
I
OH
High Level Output
Current (Note 3)
b
0.2
b
0.5
b
1.4
b
0.16
b
0.4
b
1.2
b
0.36
b
0.9
b
3.5
b
10
b
5
10
b
5
b
0.12
b
0.3
b
1.0
mA
mA
mA
I
IN
Input Current
b
0.3
0.3
b
0.3
0.3
b
1.0
1.0
m
A
m
A
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides condtions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OL
and I
OH
are tested one output at a time.
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k, t
rCL
and t
fCL
e
20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCK OPERATION
t
PHL,
t
PLH
Propagation Delay Time
Carry Out Line
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
415
160
130
800
320
250
ns
ns
ns
Carry Out Line
240
85
70
480
170
140
ns
ns
ns
C
L
e
15 pF
V
DD
e
15V
(
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
15V
(
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Decode Out Lines
500
200
160
1000
400
320
ns
ns
ns
t
TLH
, t
THL
Transition Time Carry Out
and Decode Out Lines
t
TLH
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
200
100
80
360
180
130
ns
ns
ns
t
THL
100
50
40
200
100
80
ns
ns
ns
f
CL
Maximum Clock Frequency
Measured with
Respect to Carry
Output Line
1.0
2.5
3.0
2
5
6
MHz
MHz
MHz
t
WL
, t
WH
Minimum Clock
Pulse Width
125
45
35
250
90
70
ns
ns
ns
t
rCL
, t
fCL
Clock Rise and
Fall Time
20
15
5
m
s
m
s
m
s
t
SU
Minimum Clock Inhibit
Data Setup Time
120
40
32
240
80
65
ns
ns
ns
C
IN
Average Input Capacitance
5
7.5
pF
3
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