參數(shù)資料
型號(hào)： CD4022BCMX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 計(jì)數(shù)器
中文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP RING COUNTER, PDSO16
封裝： 0.150 INCH, MS-012, SOIC-16
文件頁數(shù)： 4/7頁
文件大?。?/td> 76K
代理商： CD4022BCMX
www.fairchildsemi.com
4
C
D
40
17BC
C
D
40
22BC
AC Electrical Characteristics (Note 4)
TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Note 4: AC Parameters are guaranteed by DC correlated testing.
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line
VDD = 5V
415
800
ns
VDD = 10V
160
320
VDD = 15V
130
250
Carry Out Line
VDD = 5V
CL = 15 pF
240
480
ns
VDD = 10V
85
170
VDD = 15V
70
140
Decode Out Lines
VDD = 5V
500
1000
ns
VDD = 10V
200
400
VDD = 15V
160
320
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH
VDD = 5V
200
360
ns
VDD = 10V
100
180
VDD = 15V
80
130
tTHL
VDD = 5V
100
200
ns
VDD = 10V
50
100
VDD = 15V
40
80
fCL
Maximum Clock Frequency
VDD = 5V
Measured with
1.0
2
MHz
VDD = 10V
Respect to Carry
2.5
5
VDD = 15V
Output Line
3.0
6
tWL, tWH
Minimum Clock Pulse Width
VDD = 5V
125
250
ns
VDD = 10V
45
90
VDD = 15V
35
70
trCL, tfCL
Clock Rise and Fall Time
VDD = 5V
20
s
VDD = 10V
15
VDD = 15V
5
tSU
Minimum Clock Inhibit Data Setup Time
VDD = 5V
120
240
ns
VDD = 10V
40
80
VDD = 15V
32
65
CIN
Average Input Capacitance
57.5
pF
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RESET OPERATION
tPHL, tPLH
Propagation Delay Time
Carry Out Line
VDD = 5V
415
800
ns
VDD = 10V
160
320
VDD = 15V
130
250
Carry Out Line
VDD = 5V
240
480
ns
VDD = 10V
CL = 15 pF
85
170
VDD = 15V
70
140
Decode Out Lines
VDD = 5V
500
1000
ns
VDD = 10V
200
400
VDD = 15V
160
320
tW
Minimum Reset
VDD = 5V
200
400
ns
Pulse Width
VDD = 10V
70
140
VDD = 15V
55
110
tREM
Minimum Reset
VDD = 5V
75
150
ns
Removal Time
VDD = 10V
30
60
VDD = 15V
25
50
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