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參數(shù)資料
| 型號： | CD4021 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Stage Static Shift Register |
| 中文描述： | 8級靜態(tài)移位寄存器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 93K |
| 代理商： | CD4021 |
7-83
Specifications CD4014BMS, CD4021BMS
Propagation Delay
TPHL
TPLH
VDD = 10V
1, 2, 3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
160
ns
VDD = 15V
1, 2, 3
-
120
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
-
100
ns
VDD = 15V
1, 2, 3
-
80
ns
Maximum Clock Input
Frequency
FCL
VDD = 10V
1, 2, 3
6
-
MHz
VDD = 15V
1, 2, 3
8.5
-
MHz
Clock Rise and Fall Time
(Note 4)
TRCL
TFCL
VDD = 5V
3, 5
-
15
μ
s
VDD = 10V
3, 5
-
15
μ
s
VDD = 15V
3, 5
-
15
μ
s
Minimum Hold Time Seri-
al In, Parallel In
Parallel/Serial Control
TH
VDD = 5V
1, 2, 3
-
0
ns
VDD = 10V
1, 2, 3
-
0
ns
VDD = 15V
1, 2, 3
-
0
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
-
180
ns
VDD = 10V
1, 2, 3
-
80
ns
VDD = 15V
1, 2, 3
-
50
ns
Minimum Setup Time
Serial Input (Ref. to CL)
TS
VDD = 5V
2, 3
-
120
ns
VDD = 10V
2, 3
-
80
ns
VDD = 15V
2, 3
-
60
ns
Minimum Setup Time
Parallel Inputs
CD4014BMS
(Ref. to CL)
TS
VDD = 5V
2, 3
-
80
ns
VDD = 10V
2, 3
-
50
ns
VDD = 15V
2, 3
-
40
ns
Minimum Setup Time
Parallel Inputs
CD4021BMS
(Ref. to P/S)
TS
VDD = 5V
2, 3
+25
o
C
+25
o
C
+25
o
C
-
50
ns
VDD = 10V
2, 3
-
30
ns
VDD = 15V
2, 3
-
20
ns
Minimum Setup Time
Parallel/Serial Control
CD4014BMS (Ref. to CL)
TS
VDD = 5V
2, 3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
180
ns
VDD = 10V
2, 3
-
80
ns
VDD = 15V
2, 3
-
60
ns
Minimum P/S Pulse
Width (CD4021BMS)
TWH
VDD = 5V
2, 3
-
160
ns
VDD = 10V
2, 3
-
80
ns
VDD = 15V
2, 3
-
50
ns
Minimum P/S Removal
Time CD4021BMS
(Ref. to CL)
TREM
VDD = 5V
2, 3
-
280
ns
VDD = 10V
2, 3
-
140
ns
VDD = 15V
2, 3
-
100
ns
Input Capacitance
CIN
Any Input
1, 2
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
相關PDF資料 |
PDF描述 |
|---|---|
| CD4021BC | 8-Stage Static Shift Register |
| CD4021BCM | 8-Stage Static Shift Register |
| CD4021BCN | 8-Stage Static Shift Register |
| CD4022BC | Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs |
| CD4022BCJ | Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CD4021AD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4021AE | 制造商:Semiconductors 功能描述: 制造商:RCA 功能描述:Shift Register, 16 Pin, Plastic, DIP |
| CD4021AF/3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4021AFX | 制造商:RCA 功能描述:Shift Register, 16 Pin, Ceramic, DIP |
| CD4021AR1022 | 制造商:Harris Corporation 功能描述: |
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