參數(shù)資料
型號(hào): CD40192BM
廠商: National Semiconductor Corporation
元件分類: 通用總線功能
英文描述: Synchronous 4-Bit Up/Down Decade Counter
中文描述: 同步4位向上/向下十年計(jì)數(shù)器
文件頁數(shù): 3/6頁
文件大小: 141K
代理商: CD40192BM
DC Electrical Characteristics
CD40192BC/CD40193BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40
§
C
Min
a
25
§
C
Typ
a
85
§
C
Min
Units
Max
Min
Max
Max
I
OH
High Level Output
Current (Note 3)
V
DD
e
5V, V
O
e
4.6V
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
b
0.52
b
1.3
b
3.6
b
0.44
b
1.1
b
3.0
b
0.88
b
2.25
b
8.8
b
10
b
5
10
b
5
b
0.36
b
0.9
b
2.4
mA
mA
mA
I
IN
Input Current
b
0.3
0.3
b
0.3
0.3
b
1.0
1.0
m
A
m
A
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200 k
X
, input t
r
e
t
f
e
20 ns, unless otherwise specified.
Symbol
Parameter
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Load and Data
Inputs (A,B,C,D)
Count Up, Count
Down and Clear
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time
from Count Up or
Count Down to Q
250
100
80
400
160
130
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time
from Count Up to Carry
120
50
40
200
80
65
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time
from Count Down
to Borrow
120
50
40
200
80
65
ns
ns
ns
t
SU
Time Prior to Load
That Data Must
Be Present
100
30
25
160
50
40
ns
ns
ns
t
PHL
Propagation Delay Time
from Clear to Q
130
60
50
220
100
80
ns
ns
ns
t
PLH
or t
PHL
Propagation Delay Time
from Load to Q
300
120
95
480
190
150
ns
ns
ns
t
TLH
or t
THL
Output Transition Time
100
50
40
200
100
80
ns
ns
ns
f
CL
Maximum Count Frequency
2.5
6
7.5
4
MHz
MHz
MHz
10
12.5
t
rCL
or t
fCL
Maximum Count Rise
or Fall Time
15
5
1
m
s
m
s
m
s
t
WH
, t
WL
Minimum Count Pulse
Width
120
35
28
200
80
65
ns
ns
ns
t
WH
Minimum Clear
Pulse Width
300
120
95
480
190
150
ns
ns
ns
t
WL
Minimum Load
Pulse Width
100
40
32
160
65
55
ns
ns
ns
C
IN
Average Input Capacitance
5
7.5
pF
10
15
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacity
(Note 4)
100
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OH
and I
OL
are tested one output at a time.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application note,
AN-90.
3
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