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參數(shù)資料
| 型號(hào)： | CD40182BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Look-Ahead Carry Generator |
| 中文描述： | 查詢的CMOS超前進(jìn)位發(fā)生器 |
| 文件頁(yè)數(shù)： | 9/9頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | CD40182BMS |
7-1418
CD40182BMS
FIGURE 10. 64-BIT FULL CARRY LOOK-AHEAD ALU IN 3 LEVELS
FIGURE 11. COMBINED TWO-LEVEL LOOK-AHEAD AND RIPPLE-CARRY ALU
CnG
P
Cn
G0 P0 Cn + x
Cn + y
Cn + z
G
P
(16) CD40181BMS
CD40182BMS
CnG
P
G1 P1
CnG
P
G2 P2
CnG
P
G3 P3
CnG
P
Cn
G0 P0 Cn + x
Cn + y
Cn + z
CD40182BMS
CnG
P
G1 P1
CnG
P
G2 P2
CnG
P
G3 P3
Cn
G0 P0
Cn + x
G1 P1
Cn + y
Cn
CnG
P
G0 P0
CD40182BMS
Cn
Cn
CnG
P
Cn
G0 P0 Cn + x
Cn + y
Cn + z
CD40182BMS
CnG
P
G1 P1
Cn
G2 P2
Cn
G3 P3
Cn
Cn
CnG
P
G0 P0
CnG
P
G1 P1
Cn + x
Cn + y
CD40181BMS
Cn+4
Cn + 4
Cn + 4
G
P
CD40181BMS
G
P
Cn+4
Chip Dimensions and Pad Layout
The photographs and dimensions of each CMOS chip represent a chip when
it is part of the wafer. When the wafer is separated into individual chips, the an-
gle of cleavage may vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore, may differ slightly from the
nominal dimensions shown. The user should consider a tolerance of -3 mils to
+16 mils applicable to the nominal dimensions shown.
Dimension in parenthesis are in millimeters and are derived from the basic inch
dimensions as indicated. Grid graduations are in mils (10
inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
DIE THICKNESS:
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
0.004 inches X 0.004 inches MIN
0.0198 inches - 0.0218 inches
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