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參數(shù)資料
| 型號： | CD40181BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 4 Bit Arithmetic Logic Unit |
| 中文描述： | 的CMOS 4位算術(shù)邏輯單元 |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CD40181BMS |
7-1409
CD40181BMS
TABLE A. AC TEST SETUP REFERENCE (ACTIVE LOW DATA)
TEST DELAY TIMES
AC PATHS
DC DATA INPUTS
MODE*
INPUTS
OUTPUTS
TO VSS
TO VDD
SUMIN to SUMOUT
B0
Any F
B1, B2, B3, M, Cn
All A’s
Add
SUMIN to P
A0
P
A1, A2, A3, M, Cn
All B’s
Add
SUMIN to G
B0
G
All A’s, M, Cn
B1, B2, B3
Add
SUMIN to Cn+4
B0
Cn+4
All A’s, M, Cn
B1, B2, B3
Add
Cn to SUMOUT
Cn
Any F
All A’s, M
All B’s
Add
Cn to Cn+4
Cn
Cn+4
All A’s, M
All B’s
Add
SUMIN to A = B
B0
A = B
All A’s, B1, B2, B3, M
Cn
Subtract
SUMIN to SUMOUT (Logic Mode)
All B’s
Any F
All A’s, Cn
M
Exclusive OR
* Add Mode: S0, S3 = VDD; S1, S2 = VSS.
Subtract Mode: S0, S3 = VSS; S1, S2 = VDD.
TABLE B. MAGNITUDE COMPARISON
ACTIVE HIGH DATA
ACTIVE LOW DATA
INPUT
Cn
OUTPUT
Cn+4
MAGNITUDE
INPUT
Cn
OUTPUT
Cn+4
MAGNITUDE
1
1
A
≤
B
0
0
A
≤
B
0
1
A < B
1
0
A < B
1
0
A > B
0
1
A > B
0
0
A
≥
B
1
1
A
≥
B
1 = High level
0 = Low level
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10
-3
inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
DIE THICKNESS:
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
0.004 inches X 0.004 inches MIN
0.0198 inches - 0.0218 inches
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相關(guān)代理商/技術(shù)參數(shù) |
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| CD40182 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Look-Ahead Carry Generator |
| CD40182BCN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40182BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40182BD3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Look-Ahead Carry Generator |
| CD40182BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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