參數(shù)資料
型號: CD40175BMJ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Single 3-Input Positive-NAND Gate 6-SOT-23 -40 to 85
中文描述: 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 4/6頁
文件大?。?/td> 135K
代理商: CD40175BMJ
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k and t
r
e
t
f
e
20 ns, unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
WL
Minimum Clear Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
120
45
40
250
100
80
ns
ns
ns
t
RCL
Maximum Clock Rise Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
15
5.0
5.0
m
s
m
s
m
s
t
fCL
Maximum Clock Fall Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
15
5.0
5.0
50
50
50
m
s
m
s
m
s
f
CL
Maximum Clock Frequency
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
2.0
5.0
6.0
3.5
10
12
MHz
MHz
MHz
C
IN
Input Capacitance
Clear Input
Other Input
10
5.0
15
7.5
pF
pF
C
PD
Power Dissipation
Per Package (Note 4)
130
pF
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual
device operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OH
and I
OL
are tested one output at a time.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application
note, AN-90.
Switching Time Waveforms
TL/F/5987–3
t
r
e
t
f
e
20 ns
4
相關(guān)PDF資料
PDF描述
CD40175BCM Single 3-Input Positive AND-OR Gate 6-SC70 -40 to 85
CD40175BCN Single 3-Input Positive AND-OR Gate 6-SC70 -40 to 85
CD40175BC Quad D-Type Flip-Flop(四D觸發(fā)器)
CD40175BMS CMOS Quad D Type Flip-Flop(CMOS 四 D觸發(fā)器)
CD4017BC Decade Counter/Divider with 10 Decoded Outputs(帶10個解碼輸出的十進制計數(shù)器/除法器)
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