參數(shù)資料
型號： CD40163BMS
廠商： Intersil Corporation
英文描述： Single 2-Input Positive-AND Gate 5-SC70 -40 to 85
中文描述： 同步可編程的CMOS 4位計(jì)數(shù)器
文件頁數(shù)： 4/13頁
文件大?。?/td> 156K
代理商： CD40163BMS
4-4
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
-
-2.4
mA
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C, -
55
o
C
+25
o
C, +125
o
C, -
55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
7
-
V
Propagation Delay
Clock to Q
TPHL1
TPLH1
VDD = 10V
1, 2, 3
-
160
ns
VDD = 15V
1, 2, 3
-
120
ns
Propagation Delay
Clock to C Out
TPHL2
TPLH2
VDD = 10V
1, 2, 3
-
190
ns
VDD = 15V
1, 2, 3
-
140
ns
Propagation Delay
TE to C Out
TPHL3
TPLH3
VDD = 10V
1, 2, 3
-
110
ns
VDD = 15V
1, 2, 3
-
80
ns
Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q
TPHL4
VDD = 10V
1, 2, 3
-
220
ns
VDD = 15V
1, 2, 3
-
160
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
100
ns
VDD = 15V
1, 2, 3
-
80
ns
Maximum Clock Input Fre-
quency
FCL
VDD = 10V
1, 2, 3
5.5
-
MHz
VDD = 15V
1, 2, 3
8
-
MHz
Maximum Clock Rise or
Fall Time
TRCL
TFCL
VDD = 5V
1, 2, 3, 4
-
200
μ
s
μ
s
μ
s
VDD = 10V
1, 2, 3, 4
-
70
VDD = 15V
1, 2, 3, 4
-
15
Minimum Data Hold Time
Clock Operation
TH
VDD = 5V
1, 2, 3
-
0
ns
VDD = 10V
1, 2, 3
-
0
ns
VDD = 15V
1, 2, 3
-
0
ns
Minimum Clock Pulse
Width
Clock Operation
TW
VDD = 5V
1, 2, 3
-
170
ns
VDD = 10V
1, 2, 3
-
70
ns
VDD = 15V
1, 2, 3
-
50
ns
Minimum Setup Time
Data to Clock
TS
VDD = 5V
1, 2, 3
-
240
ns
VDD = 10V
1, 2, 3
-
90
ns
VDD = 15V
1, 2, 3
-
60
ns
Minimum Setup Time
Load to Clock
TS
VDD = 5V
1, 2, 3
-
240
ns
VDD = 10V
1, 2, 3
-
90
ns
VDD = 15V
1, 2, 3
-
60
ns
Minimum Setup Time PE
to TE to Clock
TS
VDD = 5V
1, 2, 3
-
340
ns
VDD = 10V
1, 2, 3
-
140
ns
VDD = 15V
1, 2, 3
-
100
ns
Minimum Clear Pulse
Width (CD40160BMS,
CD40161BMS)
TW
VDD = 5V
1, 2, 3
-
170
ns
VDD = 10V
1, 2, 3
-
70
ns
VDD = 15V
1, 2, 3
-
50
ns
Minimum Setup Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
TS
VDD = 5V
1, 2, 3
-
340
ns
VDD = 10V
1, 2, 3
-
140
ns
VDD = 15V
1, 2, 3
-
100
ns
Minimum Hold Time
Clear to Clock
(CD40162BMS,
CD40163BMS)
TH
VDD = 5V
1, 2, 3
+25
o
C
+25
o
C
+25
o
C
-
0
ns
VDD = 10V
1, 2, 3
-
0
ns
VDD = 15V
1, 2, 3
-
0
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
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