參數(shù)資料
型號(hào): CD40161BM
廠商: National Semiconductor Corporation
元件分類: 通用總線功能
英文描述: Decade Counter with Asynchronous Clear
中文描述: 十年的異步清除計(jì)數(shù)器
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 150K
代理商: CD40161BM
DC Electrical Characteristics
CD40160BC/CD40161BC/CD40162BC/CD40163BC (Note 2) (Continued)
Limits
a
25
§
C
Typ
Symbol
Parameter
Conditions
b
40
§
C
Min
a
85
§
C
Min
Units
Max
Min
Max
Max
V
IH
High Level Input
Voltage
V
DD
e
5V, V
O
e
0.5V or 4.5V
V
DD
e
10V, V
O
e
1V or 9V
V
DD
e
15V, V
O
e
1.5V or 13.5V
V
DD
e
5V, V
O
e
0.4V
V
DD
e
10V, V
O
e
0.5V
V
DD
e
15V, V
O
e
1.5V
V
DD
e
5V, V
O
e
4.6V
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
V
V
V
I
OL
Low Level Output
Current (Note 3)
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
I
OH
High Level Output
Current (Note 3)
b
0.52
b
1.3
b
3.6
b
0.44
b
1.1
b
3.0
b
0.88
b
2.25
b
8.8
b
10
b
5
10
b
5
b
0.36
b
0.9
b
2.4
mA
mA
mA
I
IN
Input Current
b
0.30
0.30
b
0.30
0.30
b
1.0
1.0
m
A
m
A
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k, unless otherwise specified.
Symbol
Parameter
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
All Outputs
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Any Input
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time from
Clock to Q
250
100
80
400
160
130
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time from
Clock to Carry Out
290
120
100
450
190
160
ns
ns
ns
t
PHL
or t
PLH
Propagation Delay Time from T
Enable to Carry Out
180
70
60
290
130
110
ns
ns
ns
t
PHL
Propagation Time from Clear to Q
(CD40160B, CD40161B Only)
190
80
70
300
150
120
ns
ns
ns
t
SU
Minimum Time Prior to Clock that
Data or Load must be Present
120
30
25
ns
ns
ns
t
SU
Minimum Time Prior to Clock that
Enable P or T must be Present
170
70
60
280
120
100
ns
ns
ns
t
SU
Minimum Time Prior to Clock that
Clear must be Present (CD40162B,
CD40163B Only)
120
50
40
190
80
70
ns
ns
ns
t
WL
or t
WH
Maximum Clock Pulse Width
125
45
35
250
90
70
ns
ns
ns
t
RCL
or t
FCL
Maximum Clock Rise or Fall Time
15
5.0
5.0
m
s
m
s
m
s
f
CL
Maximum Clock Frequency
2
4
MHz
MHz
MHz
5.5
7
11
14
t
THL
or t
TLH
Transition Time
100
50
40
200
100
80
ns
ns
ns
C
IN
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Average Input Capacitance
5.0
7.5
pF
Power Dissipation Capacity
(Note 4)
95
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OH
and I
OL
are tested one output at a time.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
AN-90.
3
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