參數(shù)資料
型號: CD4014BC
廠商: Fairchild Semiconductor Corporation
英文描述: 8-Stage Parallel Input/Serial Output Static Shift Register(八級并行輸入/串行輸出的靜態(tài)移位寄存器)
中文描述: 8級并行輸入/串行輸出靜態(tài)移位寄存器(八級并行輸入/串行輸出的靜態(tài)移位寄存器)
文件頁數(shù): 4/7頁
文件大小: 67K
代理商: CD4014BC
www.fairchildsemi.com
4
C
AC Electrical Characteristics
(Note 5)
T
A
=
25
°
C, input t
r
, t
f
=
20 ns, C
L
=
50 pF, R
L
=
200 k
Symbol
Parameter
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Note 6:
If more than one unit is cascaded t
rCL
should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 7:
Setup times are measured with reference to clock and a fixed hold time (t
H
) as specified.
Note 8:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
Conditions
Min
Typ
Max
Units
t
PHL
, t
PLH
Propagation Delay Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Any Input
200
320
ns
80
60
100
160
120
200
ns
ns
ns
t
THL
, t
TLH
Transition Time
50
40
4
100
80
ns
ns
MHz
f
CL
Maximum Clock
2.8
Input Frequency
6
8
12
16
90
MHz
MHz
ns
t
W
Minimum Clock
180
Pulse Width
40
25
80
50
15
ns
ns
μ
s
μ
s
μ
s
ns
t
rCL
, t
fCL
Clock Rise and
Fall Time (Note 6)
15
15
120
t
S
Minimum Set-Up Time
60
(Note 7) Serial Input
t
H
200 ns
Parallel Inputs
t
H
200 ns
40
30
80
80
60
160
ns
ns
ns
40
30
100
80
60
200
ns
ns
ns
Parallel/Serial Control
t
H
200 ns
50
40
100
80
0
ns
ns
ns
t
H
Minimum Hold Time
Serial In, Parallel In, t
S
400 ns
Parallel/Serial Control
Average Input Capacitance
10
15
7.5
ns
ns
pF
C
I
5
(Note 8)
Power Dissipation Capacitance
(Note 8)
C
PD
110
pF
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