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參數(shù)資料
| 型號： | CD4014 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Stage Static Shift Register |
| 中文描述： | 8級靜態(tài)移位寄存器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 155K |
| 代理商： | CD4014 |
DC Electrical Characteristics
CD4014BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40
§
C
a
25
§
C
a
85
§
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
OH
High Level Output
Current (Note 3)
V
DD
e
5V, V
O
e
4.6V
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
b
0.52
b
1.3
b
3.6
b
0.44
b
1.1
b
3.0
b
0.88
b
2.2
b
8
b
10
b
5
10
b
5
b
0.36
b
0.90
b
2.4
mA
mA
mA
I
IN
Input Current
b
0.3
0.3
b
0.3
0.3
b
1.0
1.0
m
A
m
A
AC Electrical Characteristics
*
T
A
e
25
§
C, input t
r
, t
f
e
20 ns, C
L
e
50 pF, R
L
e
200 k
X
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
, t
PLH
Propagation Delay Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
80
60
320
160
120
ns
ns
ns
t
THL
, t
TLH
Transition Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
f
CL
Maximum Clock
Input Frequency
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
2.8
6
8
4
MHz
MHz
MHz
12
16
t
W
Minimum Clock
Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
90
40
25
180
80
50
ns
ns
ns
t
rCL
, t
fCL
Clock Rise and
Fall Time (Note 4)
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
15
15
15
m
s
m
s
m
s
t
S
Minimum Set-Up Time
(Note 6) Serial Input
t
H
t
200 ns
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
60
40
30
120
80
60
ns
ns
ns
Parallel Inputs
t
H
t
200 ns
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
80
40
30
160
80
60
ns
ns
ns
Parallel/Serial Control
t
H
t
200 ns
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
t
H
Minimum Hold Time
Serial In, Parallel In, t
S
t
400 ns
Parallel/Serial Control
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
0
ns
ns
ns
10
15
C
I
Average Input Capacitance
(Note 5)
Any Input
5
7.5
pF
C
PD
Power Dissipation Capacitance
(Note 5)
110
pF
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OL
and I
OH
are tested one output at a time.
Note 4:
If more than one unit is cascaded t
rCL
should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated
capacitive load.
Note 5:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C family characteristics application note
AN-90.
Note 6:
Setup times are measured with reference to clock and a fixed hold time (t
H
) as specified.
3
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