參數(shù)資料
型號(hào): CD4012M
廠商: National Semiconductor Corporation
英文描述: Single 2-Input Positive-NOR Gate 5-SOT -40 to 85
中文描述: 雙4輸入或非(閃存)門
文件頁數(shù): 3/6頁
文件大?。?/td> 113K
代理商: CD4012M
DC Electrical Characteristics
CD4002C, CD4012C
Limits
a
25
§
C
Typ
Symbol
Parameter
Conditions
b
55
§
C
Min
a
85
§
C
Min
Units
Max
Min
Max
Max
I
DD
Quiescent
Device Current
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V, V
I
e
V
DD
, I
O
e
0A
V
DD
e
10V, V
I
e
V
DD
, I
O
e
0A
V
DD
e
5.0V, V
I
e
V
SS
, I
O
e
0A
V
DD
e
10V, V
I
e
V
SS
, I
O
e
0A
V
DD
e
5.0V, V
O
t
3.6V, I
O
e
0A
V
DD
e
10V, V
O
t
7.2V, I
O
e
0A
V
DD
e
5.0V, V
O
s
0.95V, I
O
e
0A
V
DD
e
10V, V
O
s
2.9V, I
O
e
0A
V
DD
e
5.0V, V
O
e
0.4V, V
I
e
V
DD
V
DD
e
10V, V
O
e
0.5V, V
I
e
V
DD
0.5
5.0
0.005
0.005
0.5
5.0
15
30
m
A
m
A
P
D
Quiescent Device
Dissipation/Package
2.5
50
0.025
0.05
2.5
50
75
300
m
W
m
W
V
OL
Output Voltage
Low Level
0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
V
OH
Output Voltage
High Level
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
V
NL
Noise Immunity
(All Inputs)
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
V
NH
Noise Immunity
(All Inputs)
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
I
D
N
Output Drive Current
N-Channel (4002)
(Note 2)
0.35
0.72
0.3
0.6
1.0
2.5
0.24
0.48
mA
mA
I
D
N
Output Drive Current
N-Channel (4012)
(Note 2)
V
DD
e
5.0V, V
O
e
0.4V, V
I
e
V
DD
V
DD
e
10V, V
O
e
0.5V, V
I
e
V
DD
0.145
0.3
0.12
0.25
0.5
0.6
0.095
0.2
mA
mA
I
D
P
Output Drive Current
P-Channel (4002)
(Note 2)
V
DD
e
5.0V, V
O
e
2.5V, V
I
e
V
SS
V
DD
e
10V, V
O
e
9.5V, V
I
e
V
SS
b
0.35
b
0.3
b
0.3
b
0.25
b
2.0
b
1.0
b
0.24
b
0.2
mA
mA
I
D
P
Output Drive Current
P-Channel (4012)
(Note 2)
V
DD
e
5.0V, V
O
e
2.5V, V
I
e
V
SS
V
DD
e
10V, V
O
e
9.5V, V
I
e
V
SS
b
0.145
b
0.35
b
0.12
b
0.3
b
0.5
b
1.2
b
0.095
b
0.24
mA
mA
I
I
Input Current
10
pA
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
I
D
N and I
D
P are tested one output at a time.
3
相關(guān)PDF資料
PDF描述
CD4012BMS CMOS NAND Gates
CD4013BCJ Single Inverter 5-SOT-23 -40 to 85
CD4013BCN Single Inverter 5-SOT-23 -40 to 85
CD4013BM Single Inverter 5-SC70 -40 to 85
CD4013BMJ Single Inverter 5-SC70 -40 to 85
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