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參數(shù)資料
| 型號： | CD40108 |
| 廠商： | Intersil Corporation |
| 英文描述： | 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 的CMOS 4 × 4多端口注冊 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 157K |
| 代理商： | CD40108 |
7-29
Specifications CD40108BMS
Minimum Clock Pulse
Width Clock or Write
Enable
TW
VDD = 5V
3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
350
ns
VDD = 10V
3
-
130
ns
VDD = 15V
3
-
90
ns
Minimum Clock Pulse
Width Write Address
TW
VDD = 5V
3
-
300
ns
VDD = 10V
3
-
150
ns
VDD = 15V
3
-
90
ns
Input Capacitance
CIN
Any Input
1, 2
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
-
25
μ
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
μ
A
1, 4
-2.8
-0.2
V
N Threshold Voltage
Delta
VTN
VDD = 10V, ISS = -10
μ
A
1, 4
-
±
1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10
μ
A
1, 4
+25
o
C
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VTP
VSS = 0V, IDD = 10
μ
A
1, 4
-
±
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
o
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
±
1.0
μ
A
Output Current (Sink)
IOL5
±
20% x Pre-Test Reading
Output Current (Source)
IOH5A
±
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD40108BMS | 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85 |
| CD40109BMS | CMOS Quad Low-to-High Voltage Level Shifter |
| CD40110 | Replaced by SN74LVCH16543A : 16-Bit Registered Transceiver With 3-State Outputs 56-SSOP -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD40108BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40108BF3A | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40108BMS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 4 x 4 Multiport Register |
| CD40109 | 制造商:Panasonic Industrial Company 功能描述:IC |
| CD40109B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CMOS QUAD LOW-TO-HIGH VOLTAGE LEVEA SHIFTER |
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