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參數(shù)資料
| 型號： | CD40106 |
| 廠商： | Intersil Corporation |
| 英文描述： | 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 施密特觸發(fā)器的CMOS六角 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 134K |
| 代理商： | CD40106 |
DC Electrical Characteristics
CD40106BC (Note 2)
Symbol
Parameter
Conditions
b
40
§
C
a
25
§
C
a
85
§
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
l
I
O
l
k
1
m
A
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
l
I
O
l
k
1
m
A
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
4.0
8.0
16.0
4.0
8.0
16.0
30
60
120
m
A
m
A
m
A
V
OL
Low Level Output
Voltage
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
V
OH
High Level Output
Voltage
4.95
9.95
14.95
4.95
9.95
14.95
5
4.95
0.95
14.95
V
V
V
10
15
V
T
b
Negative-Going Threshold
Voltage
V
DD
e
5V, V
O
e
4.5V
V
DD
e
10V, V
O
e
9V
V
DD
e
15V, V
O
e
13.5V
0.7
1.4
2.1
2.0
4.0
6.0
0.7
1.4
2.1
1.4
3.2
5.0
2.0
4.0
6.0
0.7
1.4
2.1
2.0
4.0
6.0
V
V
V
V
T
a
Positive-Going Threshold
Voltage
V
DD
e
5V, V
O
e
0.5V
V
DD
e
10V, V
O
e
1V
V
DD
e
15V, V
O
e
1.5V
3.0
6.0
9.0
4.3
8.6
12.9
3.0
6.0
9.0
3.6
6.8
10.0
4.3
8.6
12.9
3.0
6.0
9.0
4.3
8.6
12.9
V
V
V
V
H
Hysteresis (V
T
a
b
V
T
b
)
Voltage
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
1.0
2.0
3.0
3.6
7.2
10.8
1.0
2.0
3.0
2.2
3.6
5.0
3.6
7.2
10.8
1.0
2.0
3.0
3.6
7.2
10.8
V
V
V
I
OL
Low Level Output
Current (Note 3)
V
DD
e
5V, V
O
e
0.4V
V
DD
e
10V, V
O
e
0.5V
V
DD
e
15V, V
O
e
1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
I
OH
High Level Output
Current (Note 3)
V
DD
e
5V, V
O
e
4.6V
V
DD
e
10V, V
O
e
9.5V
V
DD
e
15V, V
O
e
13.5V
b
0.52
b
1.3
b
3.6
b
0.44
b
1.1
b
3.0
b
0.88
b
2.25
b
8.8
b
0.36
b
0.9
b
2.4
mA
mA
mA
I
IN
Input Current
V
DD
e
15V, V
IN
e
0V
V
DD
e
15V, V
IN
e
15V
b
0.30
0.30
b
10
b
5
10
b
5
b
0.30
0.30
b
1.0
1.0
m
A
m
A
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k, t
r
and t
f
e
20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time from
Input to Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
220
80
70
400
200
160
ns
ns
ns
t
THL
or t
TLH
Transition Time
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
C
IN
Average Input Capacitance
Any Input
5
7.5
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacity
Any Gate (Note 4)
14
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OH
and I
OL
are tested one output at a time.
Note 4:
C
PD
determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note,
AN-90.
3
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