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參數(shù)資料
| 型號： | CD22402E |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Sync Generator for TV Applications and Video Processing Systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 76K |
| 代理商： | CD22402E |
8-41
Pin Descriptions
PIN NO.
SYMBOL
DESCRIPTION
1
XRC
Delay, Genlock to Crystal Oscillator.
Resistor, diode and capacitor connection for delay that automatically
turns on the crystal oscillator when the genlock input is removed. When the signal on Terminal 1 is high the crys-
tal oscillator is inhibited. Typical values for R and C are 1M
and 0.001
μ
F. For operation as a crystal controlled
stand alone sync generator without genlock, Terminal 1 should be hardwired to V
SS
.
2
XTP
Crystal Oscillator Feedback Tap.
Feedback connection (tap) for crystal oscillator. When a crystal (shunted by
a 1M
resistor) is connected between this terminal and Terminal 23, and a 100pF capacitor is connected from
this terminal to V
SS
, the sync generator creates its own master frequency. For a 525-line, 30-frame/second ras-
ter, the crystal frequency is 504.000kHz (Note 1); and for a 625-line, 25-frame/second raster, the crystal frequen-
cy is 500.000kHz (Note 1).
3
V
SS
Negative Power Supply Voltage.
This terminal must be hardwired to Terminal 12 (V
SS
).
4
HD
Horizontal Drive Output
5
MS
Mixed Sync Output
6
C
Capacitor Connection for R-C Genlock Oscillator
7
MBB
Mixed Beam Blanking Output
8
VRE
Vertical Counter Reset to First Equalizing Pulse.
A low level signal on this terminal resets the vertical counter
to the first equalizing pulse of a field. When not in use this terminal should be connected to V
DD
.
9
VD
Vertical Drive Output
10
VRV
Vertical Counter Reset to First Vertical Sync Pulse.
A low level signal on this terminal resets the sync gen-
erator to the first vertical sync pulse of a field. For genlock operation, Terminal 10 is used as a resistor and ca-
pacitor connection for an integrator network that detects vertical sync pulses in a master sync waveform to which
the sync generator is to be genlocked. R is 22k
, and C is 0.001
μ
F. When not in use this terminal should be
connected to V
DD
.
11
HC
Horizontal Clamp Output
12
V
SS
Negative Power Supply Voltage
13
MPB
Mixed Processing Blanking Output
14
HPB
Horizontal Processing Blanking Output
15
FS2
Frame Sync Output (Odd Field).
A pulse coinciding with the first equalizing pulse is produced at the beginning
of every odd field.
16
SVD
Short Vertical Drive Output
17
VPB
Vertical Processing Blanking Output
18
SW
Operation Switch for 525-Line or 625-Line Raster.
A high level signal on Terminal 18 causes the sync gener-
ator to generate a 625-line raster. An internal pulldown resistor is connected to Terminal 18, so in the absence
of an applied input to this terminal, a 525-line raster is produced.
19
V
DD
Positive Power Supply Voltage.
V
DD
can be any voltage between +4 and +15 relative to V
SS
.
20
GEN
Genlock Input Composite Sync.
A negative going reference mixed sync waveform applied to Terminal 20 dis-
ables the crystal oscillator and locks the R-C genlock oscillator to the horizontal pulses of the reference sync
waveform. Vertical sync detection is achieved by an R-C integrator connected from Terminal 20 to Terminal 10
(vertical reset to first vertical sync pulse). An internal pull-up resistor is connected to Terminal 20 so that in the
absence of an applied input the crystal oscillator is enabled and the R-C genlock oscillator is disabled.
21
XR
Delay, Genlock to Crystal Oscillator, Resistor and Diode Connection for Delay, Genlock to Crystal Oscil-
lator.
Automatically turns on the crystal oscillator when the input to Terminal 20 is removed.
22
RC
Resistor and Capacitor Connection for Genlock Oscillator.
If the genlock oscillator is not used this terminal
should be connected to V
SS
. C should be 100pF, and R should be a 10k
potentiometer.
23
XIN
Master Frequency Input.
24
R
Resistor Connection for Genlock Oscillator.
NOTE: 32 times horizontal frequency.
CD22402
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