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參數(shù)資料
| 型號： | CD22357AE |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | CMOS Single-Chip, Full-Feature PCM CODEC |
| 中文描述： | A-LAW, PCM CODEC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CD22357AE |
4-173
CD22354A, CD22357A
A rising edge on the receive frame sync, FS
R
, will cause the
PCM data at D
R
to be latched in on the next falling edge of the
BCLK
R
. The remaining seven bits are latched on the succes-
sive seven falling edges of the bit-clock (BCLK
X
in synchronous
mode).
Transmit Section
The transmit section consists of a gain-adjustable input op-
amp, an anti-aliasing filter, a low-pass filter, a high-pass filter
and a compressing A/D converter. The input op-amp drives a
RC active anti-aliasing filter. This filter eliminates the need for
any off-chip filtering as it provides 30dB attenuation (Min) at the
sampling frequency. From this filter the signal enters a 5th order
low-pass filter clocked at 128kHz, followed by a 3rd order high-
passfilterclockat32kHz.Theoutputofthehigh-passfilterdirectly
drives the encoder capacitor ladder at an 8kHz sampling rate. A
precisionvoltagereferenceistrimmedinmanufacturingtoprovide
an input overload of nominally 2.5V
PEAK
. Transmit frame sync
pulse FS
X
controls the process. The 8-bit PCM data is clocked
out at D
X
by the BCLK
X
. BCLK
X
can be varied from 64kHz to
2.048MHz.
Receive Section
ThereceivesectionconsistsofanexpandingD/Aconverteranda
low-pass filter which fulfills both the AT&T D3/D4 specifications
and CCITT recommendations. PCM data enters the receive sec-
tion at D
R
upon the occurrence of FS
R
, Receive Frame sync
pulse. BCLK
R
, Receive Data Clock, which can range from 64kHz
to 2.048MHz, clocks the 8-bit PCM data into the receive data reg-
ister. A D/A conversion is performed on the 8-bit PCM data and
the corresponding analog signal is held on the D/A capacitor lad-
der. This signal is transferred to a switched capacitor low-pass fil-
ter clocked at 128kHz to smooth the sample-and-hold signal as
well as to compensate for the (SIN X)/X distortion.
The filter is then followed by a secondorder Sallen and Key active
filter capable of driving a 600
load to a level of 7.2dBm.
FIGURE 1. SHORT FRAME-SYNC TIMING
1
2
3
4
5
6
7
8
MCLKR
MCLKX
BCLK
X
FS
X
t
XDB
t
WWL
t
PM
t
FM
t
RM
t
WWH
t
SBFM
t
HOLD
t
HF
t
SF
t
DBD
t
DZC
t
DZC
TSX
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
BCLK
R
D
X
D
R
FS
R
t
HOLD
t
HF
t
SF
t
SDB
t
HDB
t
HBD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD22357AE WAF | 制造商:Harris Corporation 功能描述: |
| CD22357E | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD223N | 制造商:Schneider Electric 功能描述:SWITCH FUSIBLE GD 240V 100A 2P NEMA1 |
| CD22401BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| CD22401BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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