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參數(shù)資料
| 型號： | CD22357A |
| 廠商： | Intersil Corporation |
| 元件分類： | Codec |
| 英文描述： | CMOS Single-Chip, Full-Feature PCM CODEC |
| 中文描述： | CMOS單芯片，全功能的PCM編解碼器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CD22357A |
4-172
CD22354A, CD22357A
Functional Description
Power Supply Sequencing
Do not apply input signal or load on output before powering
up V
CC
supply. Care must be taken to ensure that D
X
pin
goes on common back plane (with other D
X
pins from other
chips). D
X
pin cannot drive >50mA before Power-Up. This
will cause the part to latch up.
Power-Up
When power is first applied, the Power-On reset circuitry ini-
tializes the CODEC and places it in a Power-Down mode.
When the CODEC returns to an active state from the Power-
Down mode, the receive output is muted briefly to minimize
turn-on “click”.
To power up the device, there are two methods available.
1. A logical zero at MCLK
R
/PDN will power up the device,
provided FS
X
or FS
R
pulses are present.
2. Alternatively,aclock(MCLK
R
)mustbeappliedtoMCLK
R
/
PDN and FS
X
or FS
R
pulses must be present.
Power-Down
Two power-down modes are available.
1. Alogical1atMCLK
R
/PDN,afterapproximately0.5ms,will
power down the device.
2. Alternatively, hold both FS
X
and FS
R
continuously low,
the device will power down approximately 0.5ms after the
last FS
X
or FS
R
pulse.
Synchronous Operation
(Transmit and Receive Sections use the Same Master
Clock)
The same master clock and bit-clock should be used for the
receive and transmit sections. MCLK
X
(pin 9) is used to pro-
vide the master clock for the transmit section; the receive
section will use the same master clock if the MCLK
R
/PDN
(pin 8) is grounded (synchronous operation), or at V+
(power-down mode). MCLK
R
/PDN may be clocked only if a
clock is provided at BCLK
R
/CLKSEL (pin 7) as in asynchro-
nous operation.
The BCLK
X
(pin 10) is used to provide the bit clock to the
transmit section. In synchronous operation, this bit clock is
also used for the receive section if MCLK
R
/PDN (pin 8) is
grounded. BCLK
R
/CLKSEL (pin 7) is then used to select the
proper internal frequency division for 1.544MHz, 1.536MHz
or 2.048MHz operation (see Table below). For 1.544MHz
operation, the device automatically compensates for the
193rd clock pulse each frame.
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the leading edge of BCLK
X
. After 8 bit-
clock periods, the tristate D
X
output is returned to a high
impedance state. With an FS
R
pulse, PCM data is latched
via the D
R
input on the negative edge of the BCLK
X
. FS
X
and FS
R
must be synchronous with MCLK
X
.
Asynchronous Operation
(Transmit and Receive Sections use Separate Master
Clocks)
For the CD22357A, the MCLK
X
and MCLK
R
must be
2.048MHz and for the CD22354A must be 1.536MHz or
1.544MHz. These clocks need not be synchronous. However,
for best transmission performance, it is recommended that
MCLK
X
and MCLK
R
be synchronous.
For 1.544MHz operation the device automatically compensates
for the 193rd clock pulse each frame. FS
X
starts the encoding
operation and must be synchronous with MCLK
X
and BCLK
X
.
FS
R
starts the decoding operation and must be synchronous
with BCLK
R
. BCLK
R
must be clocked in asynchronous opera-
tion. BCLK
X
and BCLK
R
may be between 64kHz - 2.04MHz.
Short-Frame Sync Mode
When the power is first applied, the power initialization circuitry
places the CODEC in a short-frame sync mode. In this mode
both frame sync pulses must be 1 bit-clock period long, with the
timing relationship shown in Figure 1.
With FS
X
high during the falling edge of the BCLK
X
, the next
rising edge of BCLK
X
enables the D
X
tristate output buffer,
which will output the sign bit. The following rising seven edges
clock out the remaining seven bits upon which the next falling
edge will disable the D
X
output.
With FS
R
high during the falling edge of the BCLK
R
(BCLK
X
in
synchronous mode), the next falling edge of BCLK
R
latches in
the sign bit. The following seven edges latch in the seven
remaining bits.
Long-Frame Sync Mode
In this mode of operation, both of the frame sync pulses must
be three or more bit-clock periods long with the timing relation-
ship shown in Figure 2.
Based on the transmit frame sync FS
X
, the CODEC will sense
whether short or long-frame sync pulses are being used.
For 64kHz operation the frame sync pulse must be kept low for
a minimum of 160ns.
TheD
X
tristateoutputbufferisenabledwiththerisingedgeofFS
X
or the rising edge of the BCLK
X
, whichever comes later and the
firstbitclockedoutisthesignbit.Thefollowingsevenrisingedges
oftheBCLK
X
clockouttheremainingsevenbits.TheD
X
outputis
disabled by the next falling edge of the BCLK
X
following the 8th
rising edge or by FS
X
going low whichever comes later.
CLOCKING OPTIONS
MODE
BCLK
R
/CLKSEL
(PIN 7)
MASTER CLOCK
FREQUENCY SELECTED
CD22354A (
μ
)
CD22357A (A)
Asynchronous
or
Synchronous
Clocked
1.536MHz or
1.544MHz
2.048MHz
Synchronous
0
2.048MHz
1.536MHz or
1.544MHz
Synchronous 1(or open circuit)
1.536MHz or
1.544MHz
2.048MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD22357AE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD22357AE WAF | 制造商:Harris Corporation 功能描述: |
| CD22357E | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD223N | 制造商:Schneider Electric 功能描述:SWITCH FUSIBLE GD 240V 100A 2P NEMA1 |
| CD22401BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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