
4-233
CD22301
Output Pulse Fall Time
t
F
4, 8
9, 10
-
-
40
ns
Output Pulse Width
t
W
4, 8
9, 10
290
324
340
ns
Pulse Width Differential
t
W
4, 8
9, 10
-10
0
10
ns
Clock Drive Current
I
CL
-
2
-
mA
NOTES:
1. No signal input. Measure voltage between pins 7 and 8.
2. Measure clock limiter input impedance at pin 15. See Figure 5.
3. Adjust potentiometer for 0V (See Figure 5). Measure ALBO off impedances from pins 2, 3 and 4 to pin 1.
4. Increase potentiometer until voltage at pin 17 = 2V (See Figure 5). Measure ALBO on impedances from pins 2, 3 and 4 to pin 1.
5. Adjust potentiometer for
V = 0V (See Figure 6). Then slowly increase
V in the positive direction until pulses are observed at the DATA
terminal.
6. Continue increasing
V until the DC level at the clock terminal drops to 4V (See Figure 6).
7. Continue increasing
V until the ALBO terminal rises to 1V (See Figure 6).
8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6 and 7.
9. Set e
IN
= 2.75mV
RMS
at f
≈
1.185MHz. Adjust frequency until maximum amplitude is obtained at pin 15. Observe output pulses at pins
10 and 11.
10. Adjust input signal amplitude until pulses just appear in outputs. Increase input amplitude by 3dB.
Electrical Specifications
T
A
= 25
o
C, V
CC
= 5.1V
±
5%
(Continued)
PARAMETER
SYMBOL
FIGURE
NOTE
MIN
TYP
MAX
UNITS
9
8
7
6
5
3
2
4
1
18
17
16
15
14
11
10
12
13
FF
FF
TIMING
PULSE
AMPLIFIER
LIMITER
CLOCK
CIRCUIT
SEE FIG. 2
ALBO
OUTPUT
CIRCUIT
SEE
FIG. 1
GATE
GATE
AO1
AO2
AO3
0.1
μ
F
PULSE
INPUT
430
1.8K
8.2K
2.7K
470
μ
H
2200pF
510
82pF
0.1
μ
F
0.1
μ
F
4.53K
1.33K
150pF
6.19K
15
μ
H
1500pF
ALBO
GND
SUBSTRATE
ALBO
BIAS
1
μ
F
+
PEAK
DETECTOR
CLOCK THRESHOLD
COMPARATOR
DATA THRESHOLD
COMPARATOR
17
μ
H
0.1
μ
F
600 - 800pF
120K
BIAS
LC TANK
INPUT
V
CC
V
EE
V
CC
100
μ
H
PHASE
SHIFT
NETWORK
PULSE
OUTPUT
3.83K
33pF
PRE-
AMPLIFIER
130
FIGURE 1. TYPICAL 1.544MHz T1 REPEATER SYSTEM