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參數(shù)資料
| 型號： | CAT706SVI-G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 133K |
| 代理商： | CAT706SVI-G |
CAT705, CAT706, CAT813
http://onsemi.com
6
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 2. VCC Supply Current vs. Temperature
Figure 3. Normalized Reset Threshold Voltage
vs. Temperature
TEMPERATURE (°C)
100
80
60
40
20
0
20
40
1
2
3
4
5
6
8
9
100
80
60
40
20
0
20
40
0.94
0.96
0.98
1.00
1.02
1.04
1.06
SUPPL
Y
CURRENT
(m
A)
NORMALIZED
RESET
THRESHOLD
(V)
120
7
FUNCTIONAL DESCRIPTION
Processor Reset
The CAT705, CAT706 & CAT813 detect supply voltage
(VCC) conditions that are below the specified voltage trip
value (VRST) and provide a reset output to maintain correct
system operation. On powerup, RESET (or RESET for the
CAT813) are kept active for a minimum delay tRP of 140 ms
after the supply voltage (VCC) rises above VRST to allow the
power supply and processor to stabilize. When VCC drops
below the voltage trip value (VRST), the reset output signals
RESET (or RESET) are pulled active. RESET (or RESET)
is specifically designed to provide the reset input signals for
processors. This provides reliable and consistent operation
as power is turned on, off or during brownout conditions by
maintaining the processor operation in known conditions.
Manual Reset
The CAT705, CAT706 & CAT813 each have a Manual
Reset (MR) input to allow for alternative control of the reset
outputs. The MR input is designed for direct connection to
a pushbutton (see Figure 4). The MR input is internally
pulled up by 60 k
W resistor and must be pulled low to cause
the reset output to go active. Internally, this input is
debounced and timed such that RESET (or RESET) signals
of at least 140 ms minimum will be generated. The min
140 ms tRP delay commences as the Manual Reset input is
released from the low level. (see Figure 5).
WDI
GND
PFI
CAT705
CAT706
CAT813
Figure 4. Pushbutton RESET
VCC
MR
PFO
WDO
RESET/RESET
RESET
Figure 5. Timing Diagram – Pushbutton RESET
RESET
MR
VIL
tPB
tPDLY
VIH
tRP
VOH
VOL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT706SVI-GT3 | 功能描述:監(jiān)控電路 Microprocessor Super Circuit RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT706SZGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT706SZI-G | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:レP Supervisory Circuits |
| CAT706SZI-GT3 | 功能描述:監(jiān)控電路 MPU SUPR CIRCUIT RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT706TVI-G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:μP Supervisory Circuits |
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