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參數(shù)資料
| 型號： | CAT64LC40ZS-TE7 |
| 英文描述： | 72-Mbit QDR™-II SRAM 4-Word Burst Architecture |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC40ZS-TE7 |
9
CAT64LC10/20/40
Doc. No. 1021, Rev. A
RESET
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High-
Z condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/
BSY
pin and on
the DO pin if
CS
is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
ERASE/WRITE ENABLE and DISABLE
The CAT64LC10/20/40 powers up in the erase/write
disabled state. After power-up or while the device is in an
erase/write disabled state, any write operation must be
preceded by an execution of the EWEN instruction.
Once enabled, the device will stay enabled until an
EWDS has been executed or a power-down has occured.
The EWDS is used to prevent any inadvertent over-
writing of the data. The EWEN and EWDS instructions
have no affect on the READ operation and are not
affected by the RESET input.
Figure 8. EWDS Instruction Timing
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
SK
DI
CS
DO
RESET
1
0
1
0
0
0
0
0
HIGH-Z
HIGH
RDY/
BUSY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC10WITE13 | 1K/2K/4K-Bit SPI Serial EEPROM |
| CAT64LC10WTE13 | 1K/2K/4K-Bit SPI Serial EEPROM |
| CAT64LC10YATE13 | 1K/2K/4K-Bit SPI Serial EEPROM |
| CAT64LC10YITE13 | 1K/2K/4K-Bit SPI Serial EEPROM |
| CAT64LC10YRATE13 | 1K/2K/4K-Bit SPI Serial EEPROM |
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|---|---|
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| CAT6-5P0E-MF | 制造商:Sola/Hevi-Duty 功能描述:SPD CAT6 RJ45 MF |
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