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參數(shù)資料
| 型號： | CAT5132ZI-10-GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DPP 15V 128TAP I2C 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
CAT5132
http://onsemi.com
10
Data Register (DR)
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB bit
as a “0”. Writing to the DR is performed in the same fashion
as the WCR except that a time delay of up to 5 ms is
experienced while the nonvolatile store operation is being
performed. During the internal non-volatile write cycle, the
device ignores transitions at the SDA and SCL pins, and the
SDA output is at a high impedance state. The WCR is also
written during a write to DR. After a DR WRITE is complete
the DR and WCR will contain the same wiper position.
To write or read to the DR, first the access to DR is
selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 17) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes the CAT5132 responds with an acknowledge. At
this time the data is written both to volatile and non-volatile
registers, then the device enters its standby state.
Table 17. DR WRITE OPERATION
0
00
0
ST
1
1A
0
1
0
A
A SP
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
DR(00h) selection
0
00
0
ST
1
1A
0
A
A SP
XX
X
ACK
ST
OP
ACK
ST
AR
T
slave address byte
DR address 00h
data byte
A read operation (see Table 18) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read.
After each of the three bytes the CAT5132 responds with an
acknowledge and then the device transmits the data byte.
The master terminates the read operation by issuing a STOP
condition following the last bit of Data byte.
Table 18. DR READ OPERATION
0
00
0
ST
1
1A
0
1
0
A
A SP
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
DR(00h) selection
0
00
0
ST
1
1A
0
ACK
ST
AR
T
slave address byte
DR address 00h
0
00
0
1
ST
1
1A
0
X
SP
ST
OP
ST
AR
T
slave address byte
data byte
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