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參數(shù)資料
| 型號(hào)： | CAT512J-TE13 |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 71K |
| 代理商： | CAT512J-TE13 |
CAT512
8/00
2
Advanced Information
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND ...................................... –0.5V to +7V
Inputs
CLK to GND ............................ –0.5V to VDD +0.5V
CS to GND .............................. –0.5V to VDD +0.5V
DI to GND ............................... –0.5V to VDD +0.5V
RDY/BSY to GND ................... –0.5V to VDD +0.5V
PROG to GND ........................ –0.5V to VDD +0.5V
VREFH to GND ........................ –0.5V to VDD +0.5V
VREFL to GND ......................... –0.5V to VDD +0.5V
Outputs
D0 to GND ............................... –0.5V to VDD +0.5V
VOUT 1– 2 to GND ................... –0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0
°C to +70°C
Industrial (‘I’ suffix) ...................... – 40
°C to +85°C
Junction Temperature ..................................... +150
°C
Storage Temperature ....................... –65
°C to +150°C
Lead Soldering (10 sec max) .......................... +300
°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
DC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Test Method
VZAP(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
ILTH(1)(2)
Latch-Up
100
mA
JEDEC Standard 17
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
—
Bits
Accuracy
INL
Integral Linearity Error
ILOAD = 250 nA, TR = C
—
0.6
± 1
LSB
TR = I
—
0.6
± 1
LSB
ILOAD = 1 A,
TR = C
—
1.2
—
LSB
TR = I
—
1.2
—
LSB
DNL
Differential Linearity Error
ILOAD = 250 nA, TR = C
—
0.25
± 0.5
LSB
TR = I
—
0.25
± 0.5
LSB
ILOAD = 1 A,
TR = C
—
0.5
—
LSB
TR = I
—
0.5
—
LSB
Logic Inputs
IIH
Input Leakage Current
VIN = VDD
——
10
A
IIL
Input Leakage Current
VIN = 0V
—
–10
A
VIH
High Level Input Voltage
2
—
VDD
V
VIL
Low Level Input Voltage
0
—
0.8
V
References
VRH
VREFH Input Voltage Range
2.7
—
VDD
V
VRL
VREFL Input Voltage Range
GND
—
VDD -2.7
V
ZIN
VREFH–VREFL Resistance
—
28K
—
VIN / RIN
Input Resistance Match
—
± 0.5
± 1%
Logic Outputs
VOH
High Level Output Voltage
IOH = – 40 AVDD–0.3
—
V
VOL
Low Level Output Voltage
IOL = 1 mA, VDD = +5V
—
0.4
V
IOL = 0.4 mA, VDD = +3V
—
0.4
V
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