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參數(shù)資料
| 型號(hào)： | CAT504 |
| 英文描述： | 8-Bit Quad DACpot |
| 中文描述： | 8位四路DACpot |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 141K |
| 代理商： | CAT504 |
CAT504
5
Doc. No. 25048-0A 2/98 M-1
PIN DESCRIPTION
Pin
Name
Function
1
2
3
4
5
6
7
V
DD
CLK
V
PP
CS
DI
DO
PROG
Power supply positive.
Clock input pin
EEPROM Programming Voltage
Chip Select
Serial data input pin.
Serial data output pin.
EEPROM Programming Enable
Input
Power supply ground.
Minimum DAC output voltage.
DAC output channel 4.
DAC output channel 3.
DAC output channel 2.
DAC output channel 1.
Maximum DAC output voltage.
8
9
10
11
12
13
14
GND
V
REF
L
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
REF
H
DEVICE OPERATION
The CAT504 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.
DIGITAL INTERFACE
The CAT504 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT504’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT504’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT504’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
DAC addressing is as follows:
DAC OUTPUT
A0
A1
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
0
0
1
0
0
1
1
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| CAT504JITE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:8-Bit Quad DACpot |
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